259 lines
6.3 KiB
C
259 lines
6.3 KiB
C
/*++
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Copyright (c) 1990-1995 Microsoft Corporation
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Module Name:
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nnclk.c
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Abstract:
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This module contains the code to set the number nine clock.
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "s3.h"
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#if defined(ALLOC_PRAGMA)
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#pragma alloc_text(PAGE, calc_clock)
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#pragma alloc_text(PAGE, gcd)
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#pragma alloc_text(PAGE, set_clock)
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#endif
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#define PROM_WRITE_INDEX 0x51
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#define PROM_WRITE_BIT 0x80
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#define SSW_READ_ENBL_INDEX 0x55
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#define SSW_READ_ENBL_BIT 0x04
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#define SSW_READ_PORT 0x03C8
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#define SSW_WRITE_INDEX 0x5C
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#define LOCK_INDEX 0x39
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#define UNLOCK_PATTERN 0xA0
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#define LOCK_INDEX2 0x38
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#define UNLOCK_PATTERN2 0x48
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#define BIOS_32K_INDEX 0x31
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#define BIOS_32K_BIT 0x80
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#define MODE_CTRL_INDEX 0x42
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#define GOPA_FLSEL 0x40
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#define GOPB_ENABLE 0x80
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#define GOPB_SLED 0x40
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#define GOPB_FLSEL 0x20
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#define GOPB_BURN 0x10
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#undef MIN
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#define MIN(a, b) (((a) < (b)) ? (a) : (b))
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#undef MAX
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#define MAX(a, b) (((a) > (b)) ? (a) : (b))
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#define CRYSTAL_FREQUENCY (14318180 * 2)
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#define MIN_VCO_FREQUENCY 50000000
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#define MAX_NUMERATOR 130
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#define MAX_DENOMINATOR MIN(129, CRYSTAL_FREQUENCY / 400000)
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#define MIN_DENOMINATOR MAX(3, CRYSTAL_FREQUENCY / 2000000)
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/* Set up the softswitch write value */
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#define CLOCK(x) VideoPortWritePortUchar(CRT_DATA_REG, (UCHAR)(iotemp | (x)))
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#define C_DATA 2
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#define C_CLK 1
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#define C_BOTH 3
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#define C_NONE 0
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/****************************************************************************
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* calc_clock
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*
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* Usage: clock frequency [set]
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* frequency is specified in MHz
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*
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***************************************************************************/
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long calc_clock(frequency, select)
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register long frequency; /* in Hz */
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int select;
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{
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register long index;
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long temp;
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long min_m, min_n, min_diff;
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long diff;
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int clock_m;
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int clock_n;
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int clock_p;
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min_diff = 0xFFFFFFF;
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min_n = 1;
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min_m = 1;
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/* Calculate 18 bit clock value */
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clock_p = 0;
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if (frequency < MIN_VCO_FREQUENCY)
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clock_p = 1;
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if (frequency < MIN_VCO_FREQUENCY / 2)
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clock_p = 2;
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if (frequency < MIN_VCO_FREQUENCY / 4)
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clock_p = 3;
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frequency <<= clock_p;
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for (clock_n = 4; clock_n <= MAX_NUMERATOR; clock_n++)
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{
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index = CRYSTAL_FREQUENCY / (frequency / clock_n);
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if (index > MAX_DENOMINATOR)
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index = MAX_DENOMINATOR;
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if (index < MIN_DENOMINATOR)
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index = MIN_DENOMINATOR;
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for (clock_m = index - 3; clock_m < index + 4; clock_m++)
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if (clock_m >= MIN_DENOMINATOR && clock_m <= MAX_DENOMINATOR)
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{
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diff = (CRYSTAL_FREQUENCY / clock_m) * clock_n - frequency;
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if (diff < 0)
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diff = -diff;
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if (min_m * gcd(clock_m, clock_n) / gcd(min_m, min_n) == clock_m &&
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min_n * gcd(clock_m, clock_n) / gcd(min_m, min_n) == clock_n)
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if (diff > min_diff)
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diff = min_diff;
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if (diff <= min_diff)
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{
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min_diff = diff;
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min_m = clock_m;
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min_n = clock_n;
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}
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}
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}
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clock_m = min_m;
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clock_n = min_n;
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/* Calculate the index */
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temp = (((CRYSTAL_FREQUENCY / 2) * clock_n) / clock_m) << 1;
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for (index = 0; vclk_range[index + 1] < temp && index < 15; index++)
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;
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/* Pack the clock value for the frequency snthesizer */
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temp = (((long)clock_n - 3) << 11) + ((clock_m - 2) << 1)
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+ (clock_p << 8) + (index << 18) + ((long)select << 22);
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return temp;
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}
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/******************************************************************************
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*
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*****************************************************************************/
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VOID set_clock(
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PHW_DEVICE_EXTENSION HwDeviceExtension,
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LONG clock_value) /* 7bits M, 7bits N, 2bits P */
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{
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register long index;
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register char iotemp;
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int select;
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select = (clock_value >> 22) & 3;
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/* Unlock the S3 registers */
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VideoPortWritePortUchar(CRT_ADDRESS_REG, LOCK_INDEX);
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VideoPortWritePortUchar(CRT_DATA_REG, UNLOCK_PATTERN);
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/* Shut off screen */
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VideoPortWritePortUchar(SEQ_ADDRESS_REG, 0x01);
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iotemp = VideoPortReadPortUchar(SEQ_DATA_REG);
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VideoPortWritePortUchar(SEQ_DATA_REG, (UCHAR)(iotemp | 0x20));
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/* set clock input to 11 binary */
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iotemp = VideoPortReadPortUchar(MISC_OUTPUT_REG_READ);
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VideoPortWritePortUchar(MISC_OUTPUT_REG_WRITE, (UCHAR)(iotemp | 0x0C));
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VideoPortWritePortUchar(CRT_ADDRESS_REG, SSW_WRITE_INDEX);
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VideoPortWritePortUchar(CRT_DATA_REG, 0);
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VideoPortWritePortUchar(CRT_ADDRESS_REG, MODE_CTRL_INDEX);
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iotemp = VideoPortReadPortUchar(CRT_DATA_REG) & 0xF0;
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/* Program the IC Designs 2061A frequency generator */
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CLOCK(C_NONE);
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/* Unlock sequence */
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CLOCK(C_DATA);
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for (index = 0; index < 6; index++)
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{
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CLOCK(C_BOTH);
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CLOCK(C_DATA);
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}
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CLOCK(C_NONE);
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CLOCK(C_CLK);
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CLOCK(C_NONE);
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CLOCK(C_CLK);
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/* Program the 24 bit value into REG0 */
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for (index = 0; index < 24; index++)
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{
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/* Clock in the next bit */
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clock_value >>= 1;
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if (clock_value & 1)
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{
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CLOCK(C_CLK);
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CLOCK(C_NONE);
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CLOCK(C_DATA);
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CLOCK(C_BOTH);
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}
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else
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{
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CLOCK(C_BOTH);
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CLOCK(C_DATA);
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CLOCK(C_NONE);
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CLOCK(C_CLK);
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}
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}
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CLOCK(C_BOTH);
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CLOCK(C_DATA);
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CLOCK(C_BOTH);
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/* If necessary, reprogram other ICD2061A registers to defaults */
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/* Select the CLOCK in the frequency synthesizer */
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CLOCK(C_NONE | select);
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/* Turn screen back on */
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VideoPortWritePortUchar(SEQ_ADDRESS_REG, 0x01);
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iotemp = VideoPortReadPortUchar(SEQ_DATA_REG);
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VideoPortWritePortUchar(SEQ_DATA_REG, (UCHAR) (iotemp & 0xDF));
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}
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/******************************************************************************
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* Number theoretic function - GCD (Greatest Common Divisor)
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*****************************************************************************/
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long gcd(a, b)
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register long a, b;
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{
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register long c = a % b;
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while (c)
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a = b, b = c, c = a % b;
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return b;
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}
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