96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
//
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// LOCAL PERIPHERAL BUS REGISTERS
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//
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// These values are used as offsets to the memory mapped IO base stored in
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// the HW device extension.
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//
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#define LPB_MODE_MM 0x0FF00 // LPB mode
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#define SERIAL_PORT_MM 0x0FF20 // Serial Communications Port
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#define UNLOCK_SEQREG 0x08 // Unlock Extended Sequencer
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#define UNLOCK_SEQ 0x06 // unlock accessing to all S3 extensions to
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// the standard VGA sequencer register set
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#define SR9_SEQREG 0x09 // Extended Sequencer 9 register
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#define SRA_SEQREG 0x0A // Extended Sequencer A register
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#define SRD_SEQREG 0x0D // Extended Sequencer D register
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#define LPB_ENAB_BIT 0x01 // bit 0 of SRD is LPB enable (pin control)
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// on some chips (M65).
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#define DISAB_FEATURE_BITS 0xFC // AND mask to turn off LPB/Feature Connector
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// on ViRGE (NOT ViRGE GX).
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#define SYS_CONFIG_S3EXTREG 0x40 // System Configuration
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//
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// Bit masks for System Configuration register (CR40)
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//
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#define ENABLE_ENH_REG_ACCESS 0x01 // bit 0 set = enhanced reg access enabled
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#define EXT_MEM_CTRL1_S3EXTREG 0x53 // Extended Memory Control 1
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//
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// Bit masks for the Extended Memory Control 1 register (CR53)
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//
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#define ENABLE_OLDMMIO 0x10 // bit 4 set = enable Trio64-type MMIO
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#define ENABLE_NEWMMIO 0x08 // bit 3 set = New MMIO (relocatable) enabled
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#define GENERAL_OUT_S3EXTREG 0x5C // General Out Port
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#define EXT_DAC_S3EXTREG 0x55 // Extended DAC Control
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#define ENABLE_GEN_INPORT_READ 0x04 // On the 764, CR55 bit 2 set enables
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// General Input Port read
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//
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// defines for return information for CheckDDCType & Configure_Chip_DDC_Caps
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//
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#define NO_DDC 0
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#define DDC1 1
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#define DDC2 2
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//
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// Bit mask for Backward Compatibility Register 2 (CR33, BWD_COMPAT2_S3EXTREG)
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//
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#define DISPLAY_MODE_INACTIVE 0x01 // bit 1 set = controller is not in
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// active display area. (M3, M5, GX2)
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#define VSYNC_ACTIVE_BIT 0x04 // bit 2 set = controller is in vertical
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// retrace area (M3, M5, GX2). Paired
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// with 3?Ah bit 3 for IGA1.
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//
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// Bit masks for SYSTEM_CONTROL_REGISTER (3?A)
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//
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#define VSSL_BIT 0x08 // Bit 3 of Feature Control Register (3?A,
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// write-only 3CA) is Vertical Sync Type Select
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#define VSYNC_ACTIVE 0x08 // Bit 3 of Input Status 1 Register (3CA in
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// read-only) is Vertical Sync Active. If set,
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// then display is in the vertical retrace mode;
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// if clear, then display is in display mode.
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#define CLEAR_VSYNC 0x3F // AND mask to clear VSYNC Control bits
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// (setting normal operation).
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#define SET_VSYNC0 0x40 // OR mask to set VSYNC Control to VSYNC = 0
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#define SET_VSYNC1 0x80 // OR mask to set VSYNC Control to VSYNC = 1
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#define CLK_MODE_SEQREG 0x01 // Clocking Mode Register
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//
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// Bit mask for Clocking Mode Register (SR1)
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//
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#define SCREEN_OFF_BIT 0x20 // bit 5 set turns the screen off.
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#define SEL_POS_VSYNC 0x7F // AND mask to clear bit 7 of 3C2, selecting
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// positive vertical retrace sync pulse
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//
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// Macro to access the serial port
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//
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#define MMFF20 (PVOID) ((ULONG_PTR)(HwDeviceExtension->MmIoBase) + SERIAL_PORT_MM)
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