488 lines
13 KiB
C
488 lines
13 KiB
C
//
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// MODULE : STi3520A.H
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// PURPOSE : STi3520A related unctions
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// AUTHOR : JBS Yadawa
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// CREATED : 7/20/96
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//
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//
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// Copyright (C) 1996 SGS-THOMSON Microelectronics
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//
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//
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// REVISION HISTORY :
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//
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// DATE :
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//
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// COMMENTS :
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//
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#ifndef __STi3520A_H__
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#define __STi3520A_H__
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#define QUANT_TAB_SIZE 64
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//---- Definition of the STi35xxx memory partitioning
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#define NB_ROW_OF_MB 22 // Number of Rows of Macro blocks for B
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// pictures when optimmization is used
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#define BUF_FULL 0x480// bit buffer occupies 0x480 * 256 bytes (1.75 Mbits)
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//---- PAL
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#define PSZ_PAL 0x0980 // Picture size = 720*576*1.5 / 256 = 0x97E
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#define BUFF_A_PAL BUF_FULL+1 //
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#define BUFF_B_PAL (BUFF_A_PAL+PSZ_PAL)
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#define BUFF_C_PAL (BUFF_B_PAL+PSZ_PAL)
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//---- NTSC
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#define PSZ_NTSC 0x07F0
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#define BUFF_A_NTSC BUF_FULL+1
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#define BUFF_B_NTSC (BUFF_A_NTSC+PSZ_NTSC)
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#define BUFF_C_NTSC (BUFF_B_NTSC+PSZ_NTSC)
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//---- OSD
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#define OSD_START (BUFF_C + ((NB_ROW_OF_MB*3)/2))*32L
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#define FORWARD_PRED 0
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#define BACKWARD_PRED 1
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#define PICT 0x0000
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#define USER 0xB200
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#define SEQ 0xB300
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#define SEQ_ERR 0xB400
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#define EXT 0xB500
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#define SEQ_END 0xB700
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#define GOP 0xB800
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#define SEQ_EXT 0x10
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#define SEQ_DISP 0x20
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#define QUANT_EXT 0x30
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#define SEQ_SCAL 0x50
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#define PICT_PSV 0x70
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#define PICT_COD 0x80
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#define PICT_SCAL 0x90
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/***********************************************/
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/* definition of states of FistVsyncAfterVbv */
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/***********************************************/
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// FistVsyncAfterVbv is a 3 state variable
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// before vbv FistVsyncAfterVbv = NOT_YET_VBV
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// between vbv and following vsync FistVsyncAfterVbv = NOT_YET_VST
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// after vsync following vbv FistVsyncAfterVbv = PAST_VBV_AND_VST
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#define NOT_YET_VBV 0
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#define NOT_YET_VST 1
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#define PAST_VBV_AND_VST 2
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#define CFG_MCF 0x00
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#define CFG_CCF 0x01
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#define VID_CTL 0x02
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#define VID_TIS 0x03
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#define VID_PFH 0x04
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#define VID_PFV 0x05
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#define VID_PPR1 0x06
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#define VID_PPR2 0x07
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#define CFG_MRF 0x08
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#define CFG_MWF 0x08
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#define CFG_BMS 0x09
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#define CFG_MRP 0x0A
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#define CFG_MWP 0x0B
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#define VID_DFP 0x0C
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#define VID_RFP 0x0E
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#define VID_FFP 0x10
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#define VID_BFP 0x12
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#define VID_VBG 0x14
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#define VID_VBL 0x16
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#define VID_VBS 0x18
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#define VID_VBT 0x1A
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#define AUD_ABG 0X1C
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#define AUD_ABL 0X1E
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#define AUD_ABS 0X20
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#define AUD_ABT 0X22
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#define VID_DFS 0x24
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#define VID_DFW 0x25
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#define VID_DFA 0x26
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#define VID_XFS 0x27
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#define VID_XFW 0x28
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#define VID_XFA 0x29
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#define VID_OTP 0x2A
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#define VID_OBP 0x2B
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#define VID_PAN 0x2C
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#define VID_SCN 0x2E
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#define VID_REV 0x78
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#define CKG_PLL 0x30
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#define CKG_CFG 0x31
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#define CKG_AUD 0x32
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#define CKG_VID 0x33
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#define CKG_PIX 0x34
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#define CKG_PCM 0x35
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#define CKG_MCK 0x36
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#define CKG_AUX 0x37
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#define CKG_DRC 0x38
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#define CFG_BFS 0x39
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#define PES_AUD 0x40
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#define PES_VID 0x41
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#define PES_SPF 0x42
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#define PES_STA 0x43
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#define PES_SC1 0x44
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#define PES_SC2 0x45
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#define PES_SC3 0x46
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#define PES_SC4 0x47
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#define PES_SC5 0x48
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#define PES_TS1 0x49
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#define PES_TS2 0x4A
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#define PES_TS3 0x4B
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#define PES_TS4 0x4C
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#define PES_TS5 0x4D
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#define PES_PTS_FIFO 0x68
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#define VID_ITM 0x60
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#define VID_ITM1 0x3C
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#define VID_ITS 0x62
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#define VID_ITS1 0x3D
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#define VID_STA 0x64
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#define VID_STA1 0x3B
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#define VID_HDF 0x66
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#define CDcount 0x67
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#define SCDcount 0x68
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#define VID_HDS 0x69
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#define VID_LSO 0x6A
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#define VID_LSR 0x6B
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#define VID_CSO 0x6C
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#define VID_LSRh 0x6D
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#define VID_YDO 0x6E
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#define VID_YDS 0x6F
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#define VID_XDO 0x70
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#define VID_XDS 0x72
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#define VID_DCF 0x74
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#define VID_QMW 0x76
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#define VID_TST 0x77
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/************************************************************/
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/* Definition of STi3520A registers with STi3520 names */
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/************************************************************/
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#define HDF VID_HDF
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#define CTL VID_CTL
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#define STA VID_STA
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#define ITM VID_ITM
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#define ITM1 VID_ITM1
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#define ITS VID_ITS
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#define ITS1 VID_ITS1
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#define MRF CFG_MRF
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#define MWF CFG_MWF
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#define BMS CFG_BMS
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#define MRP CFG_MRP
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#define MWP CFG_MWP
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#define DFP VID_DFP
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#define RFP VID_RFP
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#define FFP VID_FFP
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#define BFP VID_BFP
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#define FBP VID_FBP // shares the same address as BFP
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#define BBL VID_VBL
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#define BBS VID_VBS
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#define BBG VID_VBG
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#define BBT VID_VBT
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#define DFW VID_DFW
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#define DFS VID_DFS
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#define YDO VID_YDO
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#define XDO VID_XDO
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#define YDS VID_YDS
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#define XDS VID_XDS
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#define OEP VID_OBP
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#define OOP VID_OTP
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#define LSO VID_LSO
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#define LSR VID_LSR
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#define CSO VID_CSO
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#define DCF VID_DCF
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#define QMW VID_QMW
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/*********************************************/
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/* Definition of the STi3520A Bit Position*/
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/*********************************************/
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// CFG_CCF Register bits
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#define M32 0x80
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#define M16 0x40
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#define PBO 0x20
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#define EC3 0x10
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#define EC2 0x08
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#define ECK 0x04
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#define EDI 0x02
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#define EVI 0x01
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// CFG_DRC Register bits
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#define NPD 0x40
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#define MRS 0x20
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#define SGR 0x08
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#define CLK 0x04
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#define HPD 0x02
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#define SDR 0x01
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// CFG_MCF Register bits
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#define M20 0x80
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#define RFI 0x7F
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// CTL Register bits
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#define ERU 0x80
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#define ERS 0x40
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#define CBC 0x20
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#define DEC 0x10
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#define EPR 0x08
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#define PRS 0x04
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#define SRS 0x02
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#define EDC 0x01
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#define A35 0x8000 // for STi3500A code compatibility
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// DCF Register bits
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#define OAD1 0x8000
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#define OAD0 0x4000
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#define OAM 0x2000
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#define XYE 0x1000
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#define DAM2 0x0800
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#define DAM1 0x0400
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#define DAM0 0x0200
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#define FLD 0x0100
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#define USR 0x0080
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#define PXD 0x0040
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#define EVD 0x0020
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#define EOS 0x0010
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#define DSR 0x0008
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#define VFC2 0x0004
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#define VFC1 0x0002
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#define VFC0 0x0001
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// ITM/ITS/STA Status Register bits
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#define PDE 0x8000
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#define SER 0x4000
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#define BMI 0x2000
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#define HFF 0x1000
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#define RFF 0x0800
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#define WFE 0x0400
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#define PID 0x0200
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#define PER 0x0100
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#define PSD 0x0080
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#define TOP 0x0040
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#define BOT 0x0020
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#define BBE 0x0010
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#define BBF 0x0008
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#define HFE 0x0004
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#define BFF 0x0002
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#define HIT 0x0001
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// VID_TIS Register bits
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#define MP2 0x40
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#define SKP1 0x20
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#define SKP0 0x10
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#define OVW 0x08
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#define FIS 0x04
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#define RPT 0x02
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#define EXE 0x01
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#define SOS 0x08
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#define QMN 0x04
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#define QMI 0x02
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#define HDS 0x01
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//ckw start
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// AUD Registers
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#define AUD_ANC0 0x86
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#define AUD_ANC8 0x87
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#define AUD_ANC16 0x88
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#define AUD_ANC24 0x89
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#define AUD_ESC0 0x8A
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#define AUD_ESC8 0x8B
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#define AUD_ESC16 0x8C
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#define AUD_ESC24 0x8D
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#define AUD_ESC32 0x8E
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#define AUD_ESCX0 0x8F
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#define AUD_LRP 0x91
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#define AUD_FFL0 0x94
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#define AUD_FFL8 0x95
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#define AUD_P18 0x96
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#define AUD_CDI0 0x98
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#define AUD_FOR 0x99
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#define AUD_ITR0 0x9A
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#define AUD_ITR8 0x9B
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#define AUD_ITM0 0x9C
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#define AUD_ITM8 0x9D
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#define AUD_LCA 0x9E
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#define AUD_EXT 0x9F
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#define AUD_RCA 0xA0
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#define AUD_SID 0xA2
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#define AUD_SYN 0xA3
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#define AUD_IDE 0xA4
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#define AUD_SCM 0xA5
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#define AUD_SYS 0xA6
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#define AUD_SYE 0xA7
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#define AUD_LCK 0xA8
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#define AUD_CRC 0xAA
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#define AUD_SEM 0xAC
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#define AUD_PLY 0xAE
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#define AUD_MUT 0xB0
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#define AUD_SKP 0xB2
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#define AUD_ISS 0xB6
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#define AUD_ORD 0xB8
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#define AUD_LAT 0xBC
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#define AUD_RES 0xC0
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#define AUD_RST 0xC2
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#define AUD_SFR 0xC4
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#define AUD_DEM 0xC6
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#define AUD_IFT 0xD2
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#define AUD_SCP 0xD3
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#define AUD_ITS 0xDB
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#define AUD_IMS 0xDC
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#define AUD_HDR0 0xDE
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#define AUD_HDR8 0xDF
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#define AUD_HDR16 0xE0
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#define AUD_HDR24 0xE1
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#define AUD_PTS0 0xE2
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#define AUD_PTS8 0xE3
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#define AUD_PTS16 0xE4
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#define AUD_PTS24 0xE5
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#define AUD_PTS32 0xE6
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#define AUD_ADA 0xEC
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#define AUD_REV 0xED
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#define AUD_DIV 0xEE
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#define AUD_DIF 0xEF
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#define AUD_BBE 0xF0
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//ckw end
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//*************************************************
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// STi4500 register definitions
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//*************************************************
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#define ANC 0x06
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#define ANC_AV 0x6C
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#define ATTEN_L 0x1E
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#define ATTEN_R 0x20
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#define AUDIO_ID 0x22
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#define AUDIO_ID_EN 0x24
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#define BALE_LIM_H 0x69
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#define BALF_LIM_H 0x6B
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#define CRC_ECM 0x2A
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#define DIF 0x6F
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#define DMPH 0x46
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#define DRAM_EXT 0x3E
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#define DUAL_REG 0x1F
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#define FIFO_IN_TRESHOLD 0x52
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#define FORMAT 0x19
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#define FRAME_NUMBER 0x13
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#define FRAME_OFFSET 0x12
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#define FREE_FORM_H 0x15
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#define FREE_FORM_L 0x14
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#define HEADER 0x5E
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#define INTR 0x1A
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#define INTR_EN 0x1C
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#define INVERT_LRCLK 0x11
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#define INVERT_SCLK 0x53
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#define LATENCY 0x3C
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#define MUTE 0x30
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#define PACKET_SYNC_CHOICE 0x23
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#define PCM_DIV 0x6E
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#define PCM_FS 0x44
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#define PCM_ORD 0x38
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#define PCM_18 0x16
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#define PLAY 0x2E
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#define PTS_0 0x62
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#define PTS_1 0x63
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#define PTS_2 0x64
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#define PTS_3 0x65
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#define PTS_4 0x66
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#define REPEAT 0x34
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#define RESET 0x40
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#define RESTART 0x42
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#define SIN_EN 0x70
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#define SKIP 0x32
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#define STC_INC 0x10
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#define STC_DIVH 0x49
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#define STC_DIVL 0x48
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#define STC_CTL 0x21
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#define STC_0 0x4A
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#define STC_1 0x4B
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#define STC_2 0x4C
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#define STC_3 0x4D
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#define STC_4 0x4E
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#define STR_SEL 0x36
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#define SYNCHRO_CONFIRM 0x25
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#define SYNC_ECM 0x2C
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#define SYNC_LCK 0x28
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#define SYNC_REG 0x27
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#define SYNC_ST 0x26
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#define VERSION 0x6D
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/* Define Interrupt Masks of the STi4500*/
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#define SYNC 0x0001 // Set upon change in synchro status
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#define HEAD 0x0002 // Set when a valid header has been registered
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#define PTS 0x0004 // Set when PTS detected
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#define BALE 0x0008 // Set when under BALE treshold
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#define BALF 0x0010 // Set when over BALF treshold
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#define CRC 0x0020 // Set when CRC error is detected
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#define ANCI 0x0080 // Set when Ancillary buffer is full
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#define PCMU 0x0100 // Set on PCM buffer underflow
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#define SAMP 0x0200 // Set when sampling frequency has changed
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#define DEMP 0x0400 // Set when de-emphasis changed
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#define DFUL 0x0800 // Set when DRAM is full
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#define FIFT 0x1000 // Set when fifo_in_treshold reached
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#define FIFF 0x2000 // Set when fifo is full
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#define BOF 0x4000 // Set when Begining of frame
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#define NSYNC 0xFFFE // Set upon change in synchro status
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#define NHEAD 0xFFFD // Set when a valid header has been registered
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#define NPTS 0xFFFB // Set when PTS detected
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#define NBALE 0xFFF7 // Set when under BALE treshold
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#define NBALF 0xFFEF // Set when over BALF treshold
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#define NCRC 0xFFDF // Set when CRC error is detected
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#define NANC 0xFF7F // Set when Ancillary buffer is full
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#define NPCMU 0xFEFF // Set on PCM buffer underflow
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#define NSAMP 0xFDFF // Set when sampling frequency has changed
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#define NDEMP 0xFBFF // Set when de-emphasis changed
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#define NDFUL 0xF7FF // Set when DRAM is full
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#define NFIFT 0xEFFF // Set when fifo_in_treshold reached
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#define NFIFF 0xDFFF // Set when fifo is full
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#define NBOF 0xBFFF // Set when Begining of frame
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BOOL FARAPI VideoOpen(void);
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void FARAPI VideoClose(void);
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void FARAPI VideoInitDecoder(STREAMTYPE StreamType);
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void FARAPI VideoSetMode(WORD Mode, WORD param);
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void FARAPI VideoDecode(void);
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void FARAPI VideoStep(void);
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void FARAPI VideoBack(void);
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void FARAPI VideoStop(void);
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void FARAPI VideoPause(void);
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BOOL FARAPI AudioIsEnoughPlace(WORD size);
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BOOL FARAPI VideoIsEnoughPlace(WORD size);
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DWORD FARAPI VideoGetFirstDTS(void);
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WORD FARAPI VideoGetErrorMsg(void);
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void FARAPI VideoSkip(void);
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void FARAPI VideoRepeat(void);
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WORD FARAPI VideoGetState(void);
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DWORD FARAPI VideoGetPTS(void);
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BOOL FARAPI VideoIsFirstDTS(void);
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BOOL FARAPI VideoIsFirstField(void);
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BOOL FARAPI VideoForceBKC(BOOL bEnable);
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void FARAPI VideoMaskInt (void);
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void FARAPI VideoRestoreInt (void);
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BOOL FARAPI VideoVideoInt(void);
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WORD FARAPI SendAudioIfPossible(LPBYTE pBuffer, WORD Size);
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WORD FARAPI SendAudioToVideoIfPossible(LPBYTE Buffer, WORD Size);
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void FARAPI VideoInitPesParser(STREAMTYPE StreamType );
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BOOL FARAPI VideoIsValidPTS(void);
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DWORD FARAPI BoardReadVideoPTS(void);
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WORD FARAPI VideoTestReg(void);
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WORD FARAPI VideoTestMemPat(WORD pattern, WORD pattern1);
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WORD FARAPI VideoTestMem(void);
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void FARAPI VideoSetVideoWindow (WORD a, WORD b, WORD c, WORD d );
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void FARAPI VideoInitXY(void);
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void FARAPI SetXY(WORD xds, WORD yds);
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void FARAPI VideoSetPictureSize(void);
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void FARAPI VideoSwitchSRC (void);
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void FARAPI VideoSeekDecoder(STREAMTYPE StreamType);
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WORD FARAPI VideoGetABL(void) ;
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#endif // #ifndef __STi3520A_H
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