324 lines
7.1 KiB
C++
324 lines
7.1 KiB
C++
//***************************************************************************
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// PCI Interface(DACK) process
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//
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//***************************************************************************
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#include "common.h"
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#include "regs.h"
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#include "cdack.h"
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extern DWORD GetCurrentTime_ms( void );
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void Dack::init( const PDEVICE_INIT_INFO pDevInit )
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{
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ioBase = pDevInit->ioBase;
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}
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NTSTATUS Dack::PCIF_RESET( void )
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{
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DWORD st, et;
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UCHAR val;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, 0x80 );
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DigitalOutMode = 0x00;
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st = GetCurrentTime_ms();
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for( ; ; ) {
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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if( ( val & 0x80 ) != 0x80 )
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break;
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et = GetCurrentTime_ms();
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if( st + 10000 < et ) {
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TRAP;
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return STATUS_UNSUCCESSFUL;
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}
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}
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UCHAR initpaldata[256];
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int i;
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for( i = 0; i < 256; i++ )
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initpaldata[i] = (UCHAR)i;
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PCIF_SET_PALETTE( PALETTE_Y, initpaldata );
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PCIF_SET_PALETTE( PALETTE_Cb, initpaldata );
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PCIF_SET_PALETTE( PALETTE_Cr, initpaldata );
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return STATUS_SUCCESS;
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}
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void Dack::PCIF_AMUTE_ON( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val |= 0x40;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_AMUTE_OFF( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xbf;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_AMUTE2_ON( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val |= 0x20;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_AMUTE2_OFF( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xdf;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_VSYNC_ON( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val |= 0x10;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_VSYNC_OFF( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xef;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_PACK_START_ON( void )
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{
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WRITE_PORT_UCHAR( ioBase + PCIF_PSCNT, 0x04 );
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}
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void Dack::PCIF_PACK_START_OFF( void )
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{
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WRITE_PORT_UCHAR( ioBase + PCIF_PSCNT, 0x00 );
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}
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void Dack::PCIF_SET_DIGITAL_OUT( UCHAR mode )
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{
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DigitalOutMode = mode;
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PCIF_SET_PALETTE( PALETTE_Y, paldata[PALETTE_Y-1] );
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PCIF_SET_PALETTE( PALETTE_Cb, paldata[PALETTE_Cb-1] );
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PCIF_SET_PALETTE( PALETTE_Cr, paldata[PALETTE_Cr-1] );
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WRITE_PORT_UCHAR( ioBase + PCIF_VMODE, mode );
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WRITE_PORT_UCHAR( ioBase + PCIF_HSCNT, 0x70 );
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WRITE_PORT_UCHAR( ioBase + PCIF_VSCNT, 0x0b );
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if ( mode == 0x04 ) // S3 LPB
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WRITE_PORT_UCHAR( ioBase + PCIF_HSVS, 0x00 );
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else
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WRITE_PORT_UCHAR( ioBase + PCIF_HSVS, 0x00 );
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}
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void Dack::PCIF_SET_DMA0_SIZE( ULONG dmaSize )
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{
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UCHAR val;
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if ( dmaSize == 0 )
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return;
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dmaSize--;
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// select MTC-0
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xf8;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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// write DMA size
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCLL, (UCHAR)( dmaSize & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCLH, (UCHAR)( ( dmaSize >> 8 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCHL, (UCHAR)( ( dmaSize >> 16 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCHH, (UCHAR)( ( dmaSize >> 24 ) & 0xff ) );
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}
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void Dack::PCIF_SET_DMA1_SIZE( ULONG dmaSize )
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{
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UCHAR val;
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if ( dmaSize == 0 )
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return;
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dmaSize--;
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// select MTC-1
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xf8;
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val |= 0x04;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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// write DMA size
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCLL, (UCHAR)( dmaSize & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCLH, (UCHAR)( ( dmaSize >> 8 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCHL, (UCHAR)( ( dmaSize >> 16 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MTCHH, (UCHAR)( ( dmaSize >> 24 ) & 0xff ) );
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}
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void Dack::PCIF_SET_DMA0_ADDR( ULONG dmaAddr )
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{
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UCHAR val;
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// select MTC-0
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xf8;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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// write DMA0 address
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRLL, (UCHAR)( dmaAddr & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRLH, (UCHAR)( ( dmaAddr >> 8 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRHL, (UCHAR)( ( dmaAddr >> 16 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRHH, (UCHAR)( ( dmaAddr >> 24 ) & 0xff ) );
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}
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void Dack::PCIF_SET_DMA1_ADDR( ULONG dmaAddr )
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{
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UCHAR val;
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// select MTC-1
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xf8;
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val |= 0x04;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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// write DMA1 address
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRLL, (UCHAR)( dmaAddr & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRLH, (UCHAR)( ( dmaAddr >> 8 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRHL, (UCHAR)( ( dmaAddr >> 16 ) & 0xff ) );
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WRITE_PORT_UCHAR( ioBase + PCIF_MADRHH, (UCHAR)( ( dmaAddr >> 24 ) & 0xff ) );
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}
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void Dack::PCIF_DMA0_START( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xfc;
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val |= 0x01;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_DMA1_START( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_CNTL );
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val &= 0xfc;
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val |= 0x02;
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WRITE_PORT_UCHAR( ioBase + PCIF_CNTL, val );
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}
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void Dack::PCIF_SET_PALETTE( UCHAR select, PUCHAR pPalette )
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{
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int i;
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UCHAR val;
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ASSERT( PALETTE_Y <= select && select <= PALETTE_Cr );
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for ( i = 0; i < 256; i++ )
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paldata[select-1][i] = pPalette[i];
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val = (UCHAR)( ( READ_PORT_UCHAR( ioBase + PCIF_CPCNT ) & 0xFC ) | select | 0x04 );
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WRITE_PORT_UCHAR( ioBase + PCIF_CPCNT, val ); // clear color palette pointer
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for ( i = 0; i < 256; i++ ) {
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// DACK bug recovery. Use value from 0x07 to 0xFD in AMC mode and setting Palette Y.
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if( DigitalOutMode == 0x07 ) {
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if( select == PALETTE_Y ) {
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// convert 0x00 to 0xFF --> 0x07 to 0xFD
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// round up numbers of five and above and drop anything under five
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val = (UCHAR)(((LONG)pPalette[i] * 246 * 2 + 255) / (255 * 2) + 7);
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}
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else {
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if( pPalette[i] > 253 )
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val = 253;
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else
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val = pPalette[i];
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}
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}
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else
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val = pPalette[i];
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WRITE_PORT_UCHAR( ioBase + PCIF_CPLT, val );
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}
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}
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void Dack::PCIF_GET_PALETTE( UCHAR select, PUCHAR pPalette )
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{
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int i;
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UCHAR val;
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val = (UCHAR)( ( READ_PORT_UCHAR( ioBase + PCIF_CPCNT ) & 0xFC ) | select | 0x04 );
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WRITE_PORT_UCHAR( ioBase + PCIF_CPCNT, val ); // clear color palette pointer
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for ( i = 0; i < 256; i++ )
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pPalette[i] = READ_PORT_UCHAR( ioBase + PCIF_CPLT );
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}
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void Dack::PCIF_CHECK_SERIAL( void )
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{
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DWORD st, et;
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UCHAR val;
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st = GetCurrentTime_ms();
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for( ; ; ) {
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val = READ_PORT_UCHAR( ioBase + PCIF_SCNT );
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if( ( val & 0x80 ) != 0x80 )
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break;
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et = GetCurrentTime_ms();
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if( st + 10000 < et ) {
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TRAP;
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break;
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}
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}
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}
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void Dack::PCIF_DMA_ABORT( void )
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{
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WRITE_PORT_UCHAR( ioBase + PCIF_INTF, 0x04 );
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}
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void Dack::PCIF_ALL_IFLAG_CLEAR( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_INTF );
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val |= 0x23;
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WRITE_PORT_UCHAR( ioBase + PCIF_INTF, val );
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}
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void Dack::PCIF_ASPECT_0403( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_TEST );
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val |= 0x10;
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WRITE_PORT_UCHAR( ioBase + PCIF_TEST, val );
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}
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void Dack::PCIF_ASPECT_1609( void )
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{
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UCHAR val;
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val = READ_PORT_UCHAR( ioBase + PCIF_TEST );
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val &= 0xef;
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WRITE_PORT_UCHAR( ioBase + PCIF_TEST, val );
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}
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