954 lines
26 KiB
C
954 lines
26 KiB
C
/*
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************************************************************************
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*
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* INIT.C
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*
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*
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* Portions Copyright (C) 1996-2001 National Semiconductor Corp.
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* All rights reserved.
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* Copyright (C) 1996-2001 Microsoft Corporation. All Rights Reserved.
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*
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*
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*
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*************************************************************************
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*/
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#include "nsc.h"
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#include "newdong.h"
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#define SIR 0
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#define MIR 1
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#define FIR 2
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#define NSC_DEMO_IRDA_SPEEDS ( NDIS_IRDA_SPEED_2400 | \
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NDIS_IRDA_SPEED_2400 | \
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NDIS_IRDA_SPEED_9600 | \
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NDIS_IRDA_SPEED_19200 | \
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NDIS_IRDA_SPEED_38400 | \
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NDIS_IRDA_SPEED_57600 | \
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NDIS_IRDA_SPEED_115200 | \
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NDIS_IRDA_SPEED_1152K | \
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NDIS_IRDA_SPEED_4M )
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// NSC PC87108 index registers. See the spec for more info.
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//
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enum indexRegs {
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BAIC_REG = 0,
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CSRT_REG = 1,
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MCTL_REG = 2,
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GPDIR_REG = 3,
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GPDAT_REG = 4
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};
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#define CS_MODE_CONFIG_OFFSET 0x8
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const UCHAR bankCode[] = { 0x03, 0x08, 0xE0, 0xE4, 0xE8, 0xEC, 0xF0, 0xF4 };
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//////////////////////////////////////////////////////////////////////////
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// //
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// Function : NSC_WriteBankReg //
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// //
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// Description: //
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// Write a value to the specified register of the specified register //
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// bank. //
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// //
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//////////////////////////////////////////////////////////////////////////
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void NSC_WriteBankReg(PUCHAR comBase, UINT bankNum, UINT regNum, UCHAR val)
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{
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NdisRawWritePortUchar(comBase+3, bankCode[bankNum]);
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NdisRawWritePortUchar(comBase+regNum, val);
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// Always switch back to reg 0
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NdisRawWritePortUchar(comBase+3, bankCode[0]);
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}
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//////////////////////////////////////////////////////////////////////////
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// //
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// Function : NSC_ReadBankReg //
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// //
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// Description: //
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// Write the value from the specified register of the specified //
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// register bank. //
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// //
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//////////////////////////////////////////////////////////////////////////
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UCHAR NSC_ReadBankReg(PUCHAR comBase, UINT bankNum, UINT regNum)
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{
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UCHAR result;
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NdisRawWritePortUchar(comBase+3, bankCode[bankNum]);
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NdisRawReadPortUchar(comBase+regNum, &result);
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// Always switch back to reg 0
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NdisRawWritePortUchar(comBase+3, bankCode[0]);
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return result;
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}
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typedef struct _SYNC_PORT_ACCESS {
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PUCHAR PortBase;
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UINT BankNumber;
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UINT RegisterIndex;
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UCHAR Value;
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} SYNC_PORT_ACCESS, *PSYNC_PORT_ACCESS;
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VOID
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ReadBankReg(
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PVOID Context
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)
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{
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PSYNC_PORT_ACCESS PortAccess=(PSYNC_PORT_ACCESS)Context;
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NdisRawWritePortUchar(PortAccess->PortBase+3, bankCode[PortAccess->BankNumber]);
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NdisRawReadPortUchar(PortAccess->PortBase+PortAccess->RegisterIndex, &PortAccess->Value);
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// Always switch back to reg 0
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NdisRawWritePortUchar(PortAccess->PortBase+3, bankCode[0]);
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return;
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}
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VOID
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WriteBankReg(
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PVOID Context
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)
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{
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PSYNC_PORT_ACCESS PortAccess=(PSYNC_PORT_ACCESS)Context;
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NdisRawWritePortUchar(PortAccess->PortBase+3, bankCode[PortAccess->BankNumber]);
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NdisRawWritePortUchar(PortAccess->PortBase+PortAccess->RegisterIndex, PortAccess->Value);
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// Always switch back to reg 0
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NdisRawWritePortUchar(PortAccess->PortBase+3, bankCode[0]);
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return;
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}
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VOID
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SyncWriteBankReg(
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PNDIS_MINIPORT_INTERRUPT InterruptObject,
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PUCHAR PortBase,
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UINT BankNumber,
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UINT RegisterIndex,
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UCHAR Value
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)
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{
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SYNC_PORT_ACCESS PortAccess;
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ASSERT(BankNumber <= 7);
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ASSERT(RegisterIndex <= 7);
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PortAccess.PortBase = PortBase;
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PortAccess.BankNumber = BankNumber;
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PortAccess.RegisterIndex= RegisterIndex;
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PortAccess.Value = Value;
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NdisMSynchronizeWithInterrupt(
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InterruptObject,
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WriteBankReg,
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&PortAccess
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);
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return;
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}
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UCHAR
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SyncReadBankReg(
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PNDIS_MINIPORT_INTERRUPT InterruptObject,
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PUCHAR PortBase,
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UINT BankNumber,
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UINT RegisterIndex
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)
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{
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SYNC_PORT_ACCESS PortAccess;
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ASSERT(BankNumber <= 7);
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ASSERT(RegisterIndex <= 7);
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PortAccess.PortBase = PortBase;
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PortAccess.BankNumber = BankNumber;
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PortAccess.RegisterIndex= RegisterIndex;
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NdisMSynchronizeWithInterrupt(
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InterruptObject,
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ReadBankReg,
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&PortAccess
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);
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return PortAccess.Value;
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}
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BOOLEAN
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SyncGetDongleCapabilities(
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PNDIS_MINIPORT_INTERRUPT InterruptObject,
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UIR * Com,
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DongleParam *Dingle
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)
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{
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SYNC_DONGLE Dongle;
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Dongle.Com=Com;
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Dongle.Dingle=Dingle;
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NdisMSynchronizeWithInterrupt(
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InterruptObject,
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GetDongleCapabilities,
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&Dongle
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);
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return TRUE;
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}
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UINT
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SyncSetDongleCapabilities(
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PNDIS_MINIPORT_INTERRUPT InterruptObject,
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UIR * Com,
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DongleParam *Dingle
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)
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{
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SYNC_DONGLE Dongle;
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Dongle.Com=Com;
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Dongle.Dingle=Dingle;
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NdisMSynchronizeWithInterrupt(
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InterruptObject,
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SetDongleCapabilities,
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&Dongle
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);
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return 0;
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}
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typedef struct _SYNC_FIFO_STATUS {
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PUCHAR PortBase;
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PUCHAR Status;
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PULONG Length;
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} SYNC_FIFO_STATUS, *PSYNC_FIFO_STATUS;
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VOID
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GetFifoStatus(
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PVOID Context
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)
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{
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PSYNC_FIFO_STATUS FifoStatus=Context;
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NdisRawWritePortUchar(FifoStatus->PortBase+3, bankCode[5]);
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NdisRawReadPortUchar(FifoStatus->PortBase+FRM_ST, FifoStatus->Status);
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if (*FifoStatus->Status & ST_FIFO_VALID) {
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UCHAR High;
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UCHAR Low;
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NdisRawReadPortUchar(FifoStatus->PortBase+RFRL_L, &Low);
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NdisRawReadPortUchar(FifoStatus->PortBase+RFRL_H, &High);
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*FifoStatus->Length = Low;
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*FifoStatus->Length |= (ULONG)High << 8;
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}
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NdisRawWritePortUchar(FifoStatus->PortBase+3, bankCode[0]);
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}
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BOOLEAN
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SyncGetFifoStatus(
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PNDIS_MINIPORT_INTERRUPT InterruptObject,
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PUCHAR PortBase,
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PUCHAR Status,
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PULONG Size
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)
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{
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SYNC_FIFO_STATUS FifoStatus;
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FifoStatus.PortBase=PortBase;
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FifoStatus.Status=Status;
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FifoStatus.Length=Size;
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NdisMSynchronizeWithInterrupt(
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InterruptObject,
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GetFifoStatus,
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&FifoStatus
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);
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return (*Status & ST_FIFO_VALID);
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}
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//////////////////////////////////////////////////////////////////////////
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// //
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// Function : Ir108ConfigWrite //
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// //
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// Description: //
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// Write the data in the indexed register of the configuration I/O. //
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// //
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//////////////////////////////////////////////////////////////////////////
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void Ir108ConfigWrite(PUCHAR configIOBase, UCHAR indexReg, UCHAR data, BOOLEAN CSMode)
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{
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UCHAR IndexStore;
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if (CSMode)
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{
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NdisRawWritePortUchar(configIOBase+indexReg, data);
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NdisRawWritePortUchar(configIOBase+indexReg, data);
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}
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else
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{
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NdisRawReadPortUchar(configIOBase, &IndexStore);
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NdisRawWritePortUchar(configIOBase, indexReg);
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NdisRawWritePortUchar(configIOBase+1, data);
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NdisRawWritePortUchar(configIOBase+1, data);
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NdisRawWritePortUchar(configIOBase, IndexStore);
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}
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}
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//////////////////////////////////////////////////////////////////////////
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// //
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// Function : Ir108ConfigRead //
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// //
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// Description: //
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// Read the data in the indexed register of the configuration I/O. //
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// //
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//////////////////////////////////////////////////////////////////////////
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UCHAR Ir108ConfigRead(PUCHAR configIOBase, UCHAR indexReg, BOOLEAN CSMode)
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{
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UCHAR data,IndexStore;
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if (CSMode)
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{
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NdisRawReadPortUchar(configIOBase+indexReg, &data);
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}
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else
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{
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NdisRawReadPortUchar(configIOBase, &IndexStore);
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NdisRawWritePortUchar(configIOBase, indexReg);
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NdisRawReadPortUchar(configIOBase+1, &data);
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NdisRawWritePortUchar(configIOBase, IndexStore);
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}
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return (data);
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}
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//////////////////////////////////////////////////////////////////////////
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// //
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// Function : NSC_DEMO_Init //
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// //
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// Description: //
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// Set up configuration registers for NSC evaluation board. //
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// //
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// NOTE: //
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// Assumes configuration registers are at I/O addr 0x398. //
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// This function configures the demo board to make the SIR UART appear //
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// at <comBase>. //
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// //
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// Called By: //
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// OpenCom //
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//////////////////////////////////////////////////////////////////////////
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BOOLEAN NSC_DEMO_Init(IrDevice *thisDev)
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{
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UCHAR val;
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UCHAR FifoClear;
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BOOLEAN CSMode = FALSE;
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switch(thisDev->CardType){
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case PUMA108:
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CSMode = TRUE;
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thisDev->portInfo.ConfigIoBaseAddr = thisDev->portInfo.ioBase + CS_MODE_CONFIG_OFFSET;
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case PC87108:
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// Look for id at startup.
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if (!CSMode)
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{
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NdisRawReadPortUchar(thisDev->portInfo.ConfigIoBaseAddr, &val);
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if (val != 0x5A){
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if (val == (UCHAR)0xff){
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DBGERR(("didn't see PC87108 id (0x5A); got ffh."));
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return FALSE;
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}
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else {
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// ID only appears once, so in case we're resetting,
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// don't fail if we don't see it.
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DBGOUT(("WARNING: didn't see PC87108 id (0x5A); got %xh.",
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(UINT)val));
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}
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}
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}
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if (CSMode)
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{
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// base address ignored.
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val = 0;
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}
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else
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{
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// Select the base address for the UART
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switch ((DWORD_PTR)thisDev->portInfo.ioBase){
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case 0x3E8: val = 0; break;
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case 0x2E8: val = 1; break;
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case 0x3F8: val = 2; break;
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case 0x2F8: val = 3; break;
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default: return FALSE;
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}
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}
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val |= 0x04; // enable register banks
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val |= 0x10; // Set the interrupt line to Totempole output.
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, BAIC_REG, val, CSMode);
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// Select interrupt level according to base address,
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// following COM port mapping.
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// Also select MIR/FIR DMA channels for rcv and xmit.
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//
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switch (thisDev->portInfo.irq){
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case 3: val = 1; break;
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case 4: val = 2; break;
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case 5: val = 3; break;
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case 7: val = 4; break;
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case 9: val = 5; break;
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case 11: val = 6; break;
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case 15: val = 7; break;
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default: return FALSE;
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}
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switch (thisDev->portInfo.DMAChannel){
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case 0: val |= 0x08; break;
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case 1: val |= 0x10; break;
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case 3: val |= 0x18; break;
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default:
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DBGERR(("Bad rcv dma channel in NSC_DEMO_Init"));
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return FALSE;
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}
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, CSRT_REG, val, CSMode);
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// Select device-enable and normal-operating-mode.
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, MCTL_REG, (UCHAR)3, CSMode);
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break;
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/*
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case PC87307:
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//
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// Select Logical Device 5
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x7, 0x5);
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// Disable IO check
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,0x31,0x0);
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// Config Base address low and high.
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,
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0x61,(UCHAR)(thisDev->portInfo.ioBase));
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,
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0x60,(UCHAR)(thisDev->portInfo.ioBase >> 8));
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// Set IRQ
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,
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0x70,(UCHAR)thisDev->portInfo.irq);
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// Enable Bank Select
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,0xF0,0x82);
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// Enable UIR
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,0x30,0x1);
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break;
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*/
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case PC87308:
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// Select Logical Device 5
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x7, 0x5, FALSE);
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// Disable IO check
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,0x31,0x0, FALSE);
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// Config Base address low and high.
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,
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0x61,(UCHAR)(thisDev->portInfo.ioBasePhys), FALSE);
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,
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0x60,(UCHAR)(thisDev->portInfo.ioBasePhys >> 8), FALSE);
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// Set IRQ
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,
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0x70,(UCHAR)thisDev->portInfo.irq, FALSE);
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// Select DMA Channel
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,
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0x74,thisDev->portInfo.DMAChannel, FALSE);
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// DeSelect TXDMA Channel
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,0x75,0x4, FALSE);
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// Enable Bank Select
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,0xF0,0x82, FALSE);
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// Enable UIR
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr,0x30,0x1, FALSE);
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break;
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case PC87338:
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// Select Plug and Play mode.
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val = Ir108ConfigRead(thisDev->portInfo.ConfigIoBaseAddr, 0x1B, FALSE);
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x1B,
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(UCHAR)(val | 0x08), FALSE);
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// Write the new Plug and Play UART IOBASE register.
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x46,
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(UCHAR)((thisDev->portInfo.ioBasePhys>>2) & 0xfe), FALSE);
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x47,
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(UCHAR)((thisDev->portInfo.ioBasePhys>>8) & 0xfc), FALSE);
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// Enable 14 Mhz clock + Clk Multiplier
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x51, 0x04, FALSE);
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// Get Interrup line and shift it four bits;
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//
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val = thisDev->portInfo.irq << 4;
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// Read the Current Plug and Play Configuration 1 register.
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//
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val |= Ir108ConfigRead(thisDev->portInfo.ConfigIoBaseAddr,0x1C, FALSE);
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// Write the New Plug and Play Configuration 1 register.
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x1C, val, FALSE);
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// Setup 338 DMA.
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//
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switch (thisDev->portInfo.DMAChannel){
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case 0: val = 0x01; break;
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case 1: val = 0x02; break;
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case 2: val = 0x03; break;
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case 3:
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// Read the Current Plug and Play Configuration 3 register.
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//
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val = Ir108ConfigRead(
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thisDev->portInfo.ConfigIoBaseAddr,0x50, FALSE) | 0x01;
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// Write the new Plug and Play Configuration 3 register.
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//
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Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x50,
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val, FALSE);
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|
// Read the Current Plug and Play Configuration 3 register.
|
|
//
|
|
val = Ir108ConfigRead(
|
|
thisDev->portInfo.ConfigIoBaseAddr,0x4C, FALSE) | 0x80;
|
|
|
|
// Write the new Plug and Play Configuration 3 register.
|
|
//
|
|
Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x4C,
|
|
val, FALSE);
|
|
val = 0x04;
|
|
break;
|
|
|
|
default:
|
|
DBGERR(("Bad rcv dma channel in NSC_DEMO_Init"));
|
|
return FALSE;
|
|
}
|
|
|
|
// Write the new Plug and Play Configuration 3 register.
|
|
//
|
|
Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x4F, val, FALSE);
|
|
|
|
// Read the Current SuperI/O Configuration Register 2 register.
|
|
//
|
|
val = Ir108ConfigRead(thisDev->portInfo.ConfigIoBaseAddr,0x40, FALSE);
|
|
|
|
// Set up UIR/UART2 for Normal Power Mode and Bank select enable.
|
|
//
|
|
val |= 0xE0;
|
|
|
|
// Write the New SuperI/O Configuration Register 2 register.
|
|
//
|
|
Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x40, val, FALSE);
|
|
|
|
|
|
// Read the Current SuperI/O Configuration Register 3 register.
|
|
//
|
|
val = Ir108ConfigRead(thisDev->portInfo.ConfigIoBaseAddr,0x50, FALSE);
|
|
|
|
// Set up UIR/UART2 IRX line
|
|
//
|
|
val |= 0x0C;
|
|
|
|
// Write the New SuperI/O Configuration Register 3 register.
|
|
//
|
|
Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x50, val, FALSE);
|
|
|
|
// Set the SIRQ1 int to DRQ3 ??? only for EB
|
|
//val = Ir108ConfigRead(thisDev->portInfo.ConfigIoBaseAddr,0x4c) & 0x3f;
|
|
//Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x4c, val | 0x80);
|
|
|
|
|
|
// Read the Current Function Enable register.
|
|
//
|
|
val = Ir108ConfigRead(thisDev->portInfo.ConfigIoBaseAddr,0x00, FALSE);
|
|
|
|
// Enable UIR/UART2.
|
|
//
|
|
val |= 0x04;
|
|
|
|
// Write the New Function Enable register.
|
|
//
|
|
Ir108ConfigWrite(thisDev->portInfo.ConfigIoBaseAddr, 0x00, val, FALSE);
|
|
break;
|
|
|
|
|
|
} // End of Evaluation board configuration setction.
|
|
|
|
thisDev->UIR_ModuleId = NSC_ReadBankReg(thisDev->portInfo.ioBase, 3, 0);
|
|
|
|
if (thisDev->UIR_ModuleId<0x20)
|
|
{
|
|
// Older revs of the NSC hardware seem to handle 1MB really poorly.
|
|
thisDev->AllowedSpeedMask &= ~NDIS_IRDA_SPEED_1152K;
|
|
}
|
|
|
|
// The UART doesn't appear until we clear and set the FIFO control
|
|
// register.
|
|
|
|
NdisRawWritePortUchar(thisDev->portInfo.ioBase+2, (UCHAR)0x00);
|
|
NdisRawWritePortUchar(thisDev->portInfo.ioBase+2, (UCHAR)0x07);
|
|
|
|
// Set FIR CRC to 32 bits.
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 6, 0, 0x20);
|
|
|
|
// Switch to bank 5
|
|
// clear the status FIFO
|
|
//
|
|
NdisRawWritePortUchar(thisDev->portInfo.ioBase+3, (UCHAR)0xEC);
|
|
FifoClear = 8;
|
|
do {
|
|
NdisRawReadPortUchar(thisDev->portInfo.ioBase+6, &val);
|
|
NdisRawReadPortUchar(thisDev->portInfo.ioBase+7, &val);
|
|
NdisRawReadPortUchar(thisDev->portInfo.ioBase+5, &val);
|
|
FifoClear--;
|
|
} while( (val & 0x80) && (FifoClear > 0) );
|
|
|
|
// Test for newer silicon for support of Frame stop mode
|
|
|
|
#if 0
|
|
if (thisDev->UIR_Mid < 0x16)
|
|
// Change Bit 1 to Default 1
|
|
// 0x40 -> 0x42
|
|
#endif
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 5, 4, 0x40);
|
|
#if 0 // Since we're not currently using the multi-packet send, we don't use frame stop mode.
|
|
else
|
|
//
|
|
// Set FIFO threshold and TX_MS Tx frame end stop mode.
|
|
//
|
|
// Change Bit 1 to Default 1
|
|
// 0x68 -> 0x6a
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 5, 4, 0x60);
|
|
#endif
|
|
|
|
// Set SIR mode in IRCR1.
|
|
// Enable SIR infrared mode in the Non-Extended mode of operation
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 4, 2, 0x0C);
|
|
|
|
// Set max xmit frame size.
|
|
// Need to set value slightly larger so that counter never
|
|
// reaches 0.
|
|
//
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 4, 4,
|
|
(UCHAR)(MAX_NDIS_DATA_SIZE+1));
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 4, 5,
|
|
(UCHAR)((MAX_NDIS_DATA_SIZE+1) >> 8));
|
|
|
|
// Set max rcv frame size.
|
|
// Need to set value slightly larger so that counter never
|
|
// reaches 0.
|
|
//
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 4, 6,
|
|
(UCHAR)(MAX_RCV_DATA_SIZE+FAST_IR_FCS_SIZE));
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 4, 7,
|
|
(UCHAR)((MAX_RCV_DATA_SIZE+FAST_IR_FCS_SIZE) >> 8));
|
|
|
|
// Set extended mode
|
|
//
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 2, 2, 0x03);
|
|
|
|
// Set 32-bit FIFOs
|
|
//
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 2, 4, 0x05);
|
|
|
|
// Enable and reset FIFO's and set the receive FIF0
|
|
// equal to the receive DMA threshold. See if DMA
|
|
// is fast enough for device.
|
|
//
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 0, 2, 0x07);
|
|
|
|
// Restore to Non-Extended mode
|
|
//
|
|
NSC_WriteBankReg(thisDev->portInfo.ioBase, 2, 2, 0x02);
|
|
|
|
|
|
thisDev->portInfo.hwCaps.supportedSpeedsMask = NSC_DEMO_IRDA_SPEEDS;
|
|
thisDev->portInfo.hwCaps.turnAroundTime_usec = DEFAULT_TURNAROUND_usec;
|
|
thisDev->portInfo.hwCaps.extraBOFsRequired = 0;
|
|
|
|
// Initialize thedongle structure before calling
|
|
// GetDongleCapabilities and SetDongleCapabilities for dongle 1.
|
|
//
|
|
thisDev->currentDongle = 1;
|
|
thisDev->IrDongleResource.Signature = thisDev->DongleTypes[thisDev->currentDongle];
|
|
|
|
thisDev->IrDongleResource.ComPort = thisDev->portInfo.ioBase;
|
|
thisDev->IrDongleResource.ModeReq = SIR;
|
|
thisDev->IrDongleResource.XcvrNum = thisDev->currentDongle;
|
|
|
|
// IrDongle = GetDongleCapabilities(thisDev->IrDongleResource);
|
|
SyncGetDongleCapabilities(&thisDev->interruptObj,&thisDev->IrDongleResource,&thisDev->Dingle[0]);
|
|
|
|
// Initialize thedongle structure before calling
|
|
// GetDongleCapabilities and SetDongleCapabilities for dongle 0.
|
|
//
|
|
thisDev->currentDongle = 0;
|
|
thisDev->IrDongleResource.Signature = thisDev->DongleTypes[thisDev->currentDongle];
|
|
|
|
thisDev->IrDongleResource.ComPort = thisDev->portInfo.ioBase;
|
|
thisDev->IrDongleResource.ModeReq = SIR;
|
|
thisDev->IrDongleResource.XcvrNum = 0;
|
|
|
|
// IrDongle = GetDongleCapabilities(IrDongleResource);
|
|
SyncGetDongleCapabilities(&thisDev->interruptObj,&thisDev->IrDongleResource,&thisDev->Dingle[0]);
|
|
|
|
SyncSetDongleCapabilities(&thisDev->interruptObj,&thisDev->IrDongleResource,&thisDev->Dingle[0]);
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
#if 1
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// //
|
|
// Function: NSC_DEMO_Deinit //
|
|
// //
|
|
// DUMMY ROUTINE //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
VOID NSC_DEMO_Deinit(PUCHAR comBase, UINT context)
|
|
{
|
|
|
|
}
|
|
#endif
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// //
|
|
// Function: NSC_DEMO_SetSpeed //
|
|
// //
|
|
// Description: //
|
|
// Set up the size of FCB, the timer, FIFO, DMA and the IR mode/dongle //
|
|
// speed based on the negotiated speed. //
|
|
// //
|
|
//////////////////////////////////////////////////////////////////////////
|
|
|
|
BOOLEAN NSC_DEMO_SetSpeed(
|
|
IrDevice *thisDev,
|
|
PUCHAR comBase,
|
|
UINT bitsPerSec,
|
|
UINT context)
|
|
{
|
|
NDIS_STATUS stat;
|
|
UINT fcsSize;
|
|
|
|
LOG("==>NSC_DEMO_SetSpeed",bitsPerSec);
|
|
|
|
if (thisDev->FirReceiveDmaActive) {
|
|
|
|
thisDev->FirReceiveDmaActive=FALSE;
|
|
//
|
|
// receive dma is running, stop it
|
|
//
|
|
CompleteDmaTransferFromDevice(
|
|
&thisDev->DmaUtil
|
|
);
|
|
|
|
}
|
|
|
|
|
|
// Make sure the previous packet completely sent out(Not in the TX FIFO)
|
|
// and Txmitter is empty
|
|
// before the bandwidth control
|
|
|
|
|
|
|
|
while((SyncReadBankReg(&thisDev->interruptObj, comBase, 0, 5)& 0x60) != 0x60);
|
|
|
|
//
|
|
|
|
if (bitsPerSec > 115200){
|
|
|
|
fcsSize = (bitsPerSec >= MIN_FIR_SPEED) ?
|
|
FAST_IR_FCS_SIZE : MEDIUM_IR_FCS_SIZE;
|
|
|
|
if(bitsPerSec >= MIN_FIR_SPEED)
|
|
thisDev->IrDongleResource.ModeReq = FIR;
|
|
else
|
|
thisDev->IrDongleResource.ModeReq = MIR;
|
|
|
|
SyncSetDongleCapabilities(&thisDev->interruptObj,&thisDev->IrDongleResource,&thisDev->Dingle[0]);
|
|
|
|
|
|
// Set extended mode and set DMA fairness.
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 2, 2, 0x03);
|
|
|
|
if (thisDev->UIR_ModuleId < 0x16){
|
|
|
|
// Set Timer registers.
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 0, (UCHAR)0x2);
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 1, (UCHAR)0x0);
|
|
}
|
|
else {
|
|
|
|
// Set Timer registers timer has 8 times finer
|
|
// resolution.
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 0, (UCHAR)0xA);
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 1, (UCHAR)0x0);
|
|
}
|
|
|
|
// Set max rcv frame size.
|
|
// Need to set value slightly larger so that counter never reaches 0.
|
|
//
|
|
DBGERR(("Programming Max Receive Size registers with %d Bytes ",
|
|
MAX_RCV_DATA_SIZE+fcsSize));
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 6, (UCHAR)(MAX_RCV_DATA_SIZE+fcsSize));
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 7,
|
|
(UCHAR)((MAX_RCV_DATA_SIZE+fcsSize) >> 8));
|
|
|
|
|
|
// Reset Timer Enable bit.
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 2, 0x00);
|
|
|
|
// Set MIR/FIR mode and DMA enable
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 0, 4,
|
|
(UCHAR)((bitsPerSec >= 4000000) ? 0xA4 : 0x84));
|
|
|
|
DBGERR(("EXCR2= 0x%x",SyncReadBankReg(&thisDev->interruptObj,thisDev->portInfo.ioBase, 2, 4)));
|
|
|
|
// Set 32-bit FIFOs
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 2, 4, 0x05);
|
|
DBGERR(("EXCR2= 0x%x",SyncReadBankReg(&thisDev->interruptObj,thisDev->portInfo.ioBase, 2, 4)));
|
|
|
|
//
|
|
// We may start receiving immediately so setup the
|
|
// receive DMA
|
|
//
|
|
|
|
|
|
#if 0
|
|
// First, tear down any existing DMA
|
|
if (thisDev->FirAdapterState==ADAPTER_RX) {
|
|
|
|
thisDev->FirAdapterState=ADAPTER_NONE;
|
|
|
|
CompleteDmaTransferFromDevice(
|
|
&thisDev->DmaUtil
|
|
);
|
|
}
|
|
|
|
FindLargestSpace(thisDev, &thisDev->rcvDmaOffset, &thisDev->rcvDmaSize);
|
|
|
|
SetupRecv(thisDev);
|
|
|
|
|
|
// Set the interrupt mask to interrupt on the
|
|
// first packet received.
|
|
//
|
|
thisDev->IntMask = 0x04;
|
|
DBGOUT(("RxDMA = ON"));
|
|
#endif
|
|
}
|
|
else {
|
|
|
|
// Set SIR mode in UART before setting the timing of transciever
|
|
//
|
|
|
|
// Set SIR mode
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 4, 2, 0x0C);
|
|
|
|
// Must set SIR Pulse Width Register to 0 (3/16) as default
|
|
// Bug in 338/108
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 6, 2, 0x0);
|
|
|
|
// Clear extended mode
|
|
//
|
|
SyncWriteBankReg(&thisDev->interruptObj, comBase, 2, 2, 0x00);
|
|
|
|
|
|
thisDev->IrDongleResource.ModeReq = SIR;
|
|
SyncSetDongleCapabilities(&thisDev->interruptObj,&thisDev->IrDongleResource,&thisDev->Dingle[0]);
|
|
|
|
|
|
// Clear Line and Auxiluary status registers.
|
|
//
|
|
SyncReadBankReg(&thisDev->interruptObj, comBase, 0, 5);
|
|
SyncReadBankReg(&thisDev->interruptObj, comBase, 0, 7);
|
|
|
|
}
|
|
LOG("<==NSC_DEMO_SetSpeed",0);
|
|
return TRUE;
|
|
}
|