140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
//////////////////////////////////////////////////////////////////////////////
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//
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// (C) Philips Semiconductors 1998
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// All rights are reserved. Reproduction in whole or in part is prohibited
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// without the written consent of the copyright owner.
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//
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// Philips reserves the right to make changes without notice at any time.
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// Philips makes no warranty, expressed, implied or statutory, including but
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// not limited to any implied warranty of merchantibility or fitness for any
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// particular purpose, or that the use will not infringe any third party
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// patent, copyright or trademark. Philips must not be liable for any loss
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// or damage arising from its use.
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//
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// MPOC.H
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// Constants for MPOC
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//////////////////////////////////////////////////////////////////////////////
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#ifndef _MPOC_H_
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#define _MPOC_H_
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#define MAX_MPOC_CONTROL_REGISTERS 18
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#define MAX_MPOC_STATUS_REGISTERS 4
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// I2C Address
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#define MPOC_I2C_ADDRESS 0x8A
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// Control registers
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#define MPOC_CONTROL_REG_OFFSET 0x1D
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#define MPOC_CONTROL_REG_AGCTAKEOVER 0x1E
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#define MPOC_CONTROL_REG_HUE 0x1F
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#define MPOC_CONTROL_REG_COLOR_DECODER_0 0x20
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#define MPOC_CONTROL_REG_COLOR_DECODER_1 0x21
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#define MPOC_CONTROL_REG_VIDEO_SWITCH 0x22
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#define MPOC_CONTROL_REG_AUDIO_SWITCH 0x23
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#define MPOC_CONTROL_REG_SYNC_0 0x24
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#define MPOC_CONTROL_REG_SYNC_1 0x25
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#define MPOC_CONTROL_REG_SOUND 0x26
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#define MPOC_CONTROL_REG_VISION_IF_0 0x27
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#define MPOC_CONTROL_REG_VISION_IF_1 0x28
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#define MPOC_CONTROL_REG_VIDEO_CONTROL 0x29
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#define MPOC_CONTROL_REG_VIDEO_ADC 0x2A
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#define MPOC_CONTROL_REG_SPARE 0x2B
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#define MPOC_CONTROL_REG_AUDIO_ADC 0x2C
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#define MPOC_CONTROL_REG_FEATURES 0x2D
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#define MPOC_CONTROL_REG_IO 0x2E
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// Status registers
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#define MPOC_STATUS_REG_0 0x00
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#define MPOC_STATUS_REG_1 0x01
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#define MPOC_STATUS_REG_2 0x02
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#define MPOC_STATUS_REG_3 0x03
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#define VIDEO 0x1
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#define AUDIO 0x2
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#define MAX_AUDIO_SOURCES 0x6
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#define MAX_SOURCES 0xB
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#define MAX_VIDEO_SOURCES 0x5
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#define EXTERNAL_AGC 0x10
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// PLL demodulator setting frequency for N1D and above
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// 1/25/2000
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#define MPOC_PLL_IF_FREQ_58_POINT_75 0x00
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#define MPOC_PLL_IF_FREQ_45_POINT_75 0x20
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#define MPOC_PLL_IF_FREQ_38_POINT_90 0x40
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#define MPOC_PLL_IF_FREQ_38_POINT_00 0x60
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#define MPOC_PLL_IF_FREQ_33_POINT_40 0x80
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#define MPOC_PLL_IF_FREQ_33_POINT_90 0xc0
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typedef enum
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{
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MPOC_SRC_COMPOSITE,
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MPOC_SRC_SVHS,
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MPOC_SRC_TUNER,
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MPOC_SRC_RGB,
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MPOC_SRC_DVD,
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MPOC_SRC_AUDIO_STEREO,
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MPOC_SRC_AUDIO_EXT
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} MPOC_SRC_ENUM;
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typedef enum
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{
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MPOC_STATUS_VIDEO_IDENT,
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MPOC_STATUS_IF_PLL_LOCK,
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MPOC_STATUS_PHASE_LOCK,
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MPOC_STATUS_COLOR_IDENT,
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MPOC_STATUS_STANDARD_VIDEO,
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MPOC_STATUS_REF_OSC_LOCK,
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MPOC_STATUS_SUPPLIES_OK,
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MPOC_STATUS_AGC,
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MPOC_STATUS_RGB_INSERT,
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MPOC_STATUS_PLL_OFFSET,
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MPOC_STATUS_FM_PLL_WINDOW,
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MPOC_STATUS_FM_PLL_LOCK,
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// Additional status bits for N1D and above
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// 1/25/2000
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MPOC_STATUS_MACROVISION_SIG,
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MPOC_STATUS_IO
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}MPOC_STATUSTYPE_ENUM;
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// MPOC Video ADC mode enumeration
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typedef enum
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{
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MPOC_VIDEOADC_TV27,
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MPOC_VIDEOADC_TV32,
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MPOC_VIDEOADC_TV36,
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MPOC_VIDEOADC_VSBI,
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MPOC_VIDEOADC_VSBIQ,
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MPOC_VIDEOADC_EXT1,
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MPOC_VIDEOADC_EXT2,
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MPOC_VIDEOADC_SVGA
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}MPOC_VIDEOADC_MODE_ENUM;
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typedef union
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{
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struct
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{
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char offset;
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char buffer[MAX_MPOC_CONTROL_REGISTERS];
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}reg_set;
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char array[MAX_MPOC_CONTROL_REGISTERS+1];
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}Register;
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#endif // _MPOC_H_
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