149 lines
4.5 KiB
C
149 lines
4.5 KiB
C
#include "agp.h"
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//
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// Define the location of the GART aperture control registers
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//
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//
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// The GART registers on the 440 live in the host-PCI bridge.
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// This is unfortunate, since the AGP driver attaches to the PCI-PCI (AGP)
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// bridge. So we have to get to the host-PCI bridge config space
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// and this is only possible because we KNOW this is bus 0, slot 0.
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//
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#define AGP_440_GART_BUS_ID 0
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#define AGP_440_GART_SLOT_ID 0
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#define AGP_440LX_IDENTIFIER 0x71808086
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#define AGP_440LX2_IDENTIFIER 0x71828086
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#define AGP_440BX_IDENTIFIER 0x71908086
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#define AGP_815_IDENTIFIER 0x11308086
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#define APBASE_OFFSET 0x10 // Aperture Base Address
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#define APSIZE_OFFSET 0xB4 // Aperture Size Register
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#define PACCFG_OFFSET 0x50 // PAC Configuration Register
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#define AGPCTRL_OFFSET 0xB0 // AGP Control Register
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#define ATTBASE_OFFSET 0xB8 // Aperture Translation Table Base
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#define READ_SYNC_ENABLE 0x2000
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#define Read440Config(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalGetBusDataByOffset(PCIConfiguration, \
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AGP_440_GART_BUS_ID, \
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AGP_440_GART_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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#define Write440Config(_buf_,_offset_,_size_) \
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{ \
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ULONG _len_; \
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_len_ = HalSetBusDataByOffset(PCIConfiguration, \
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AGP_440_GART_BUS_ID, \
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AGP_440_GART_SLOT_ID, \
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(_buf_), \
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(_offset_), \
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(_size_)); \
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ASSERT(_len_ == (_size_)); \
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}
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//
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// Conversions from APSIZE encoding to MB
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//
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// 0x3F (b 11 1111) = 4MB
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// 0x3E (b 11 1110) = 8MB
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// 0x3C (b 11 1100) = 16MB
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// 0x38 (b 11 1000) = 32MB
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// 0x30 (b 11 0000) = 64MB
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// 0x20 (b 10 0000) = 128MB
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// 0x00 (b 00 0000) = 256MB
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#define AP_SIZE_4MB 0x3F
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#define AP_SIZE_8MB 0x3E
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#define AP_SIZE_16MB 0x3C
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#define AP_SIZE_32MB 0x38
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#define AP_SIZE_64MB 0x30
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#define AP_SIZE_128MB 0x20
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#define AP_SIZE_256MB 0x00
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#define AP_SIZE_COUNT 7
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#define AP_MIN_SIZE (4 * 1024 * 1024)
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#define AP_MAX_SIZE (256 * 1024 * 1024)
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#define AP_815_SIZE_COUNT 2
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#define AP_815_MAX_SIZE (64 * 1024 * 1024)
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//
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// Define the GART table entry.
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//
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typedef struct _GART_ENTRY_HW {
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ULONG Valid : 1;
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ULONG Reserved : 11;
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ULONG Page : 20;
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} GART_ENTRY_HW, *PGART_ENTRY_HW;
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//
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// GART Entry states are defined so that all software-only states
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// have the Valid bit clear.
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//
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#define GART_ENTRY_VALID 1 // 001
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#define GART_ENTRY_FREE 0 // 000
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#define GART_ENTRY_WC 2 // 010
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#define GART_ENTRY_UC 4 // 100
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#define GART_ENTRY_RESERVED_WC GART_ENTRY_WC
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#define GART_ENTRY_RESERVED_UC GART_ENTRY_UC
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#define GART_ENTRY_VALID_WC (GART_ENTRY_VALID)
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#define GART_ENTRY_VALID_UC (GART_ENTRY_VALID)
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typedef struct _GART_ENTRY_SW {
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ULONG State : 3;
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ULONG Reserved : 29;
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} GART_ENTRY_SW, *PGART_ENTRY_SW;
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typedef struct _GART_PTE {
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union {
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GART_ENTRY_HW Hard;
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ULONG AsUlong;
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GART_ENTRY_SW Soft;
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};
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} GART_PTE, *PGART_PTE;
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//
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// Define the layout of the hardware registers
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//
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typedef struct _AGPCTRL {
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ULONG Reserved1 : 7;
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ULONG GTLB_Enable : 1;
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ULONG Reserved2 : 24;
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} AGPCTRL, *PAGPCTRL;
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typedef struct _PACCFG {
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USHORT Reserved1 : 9;
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USHORT GlobalEnable : 1;
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USHORT PCIEnable : 1;
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USHORT Reserved2 : 5;
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} PACCFG, *PPACCFG;
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//
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// Define the 440-specific extension
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//
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typedef struct _AGP440_EXTENSION {
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BOOLEAN GlobalEnable;
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BOOLEAN PCIEnable;
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PHYSICAL_ADDRESS ApertureStart;
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ULONG ApertureLength;
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PGART_PTE Gart;
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ULONG GartLength;
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PHYSICAL_ADDRESS GartPhysical;
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ULONGLONG SpecialTarget;
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} AGP440_EXTENSION, *PAGP440_EXTENSION;
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