213 lines
6.9 KiB
C
213 lines
6.9 KiB
C
#include "agp.h"
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#define PCI_ADDRESS_MEMORY_ADDRESS_MASK_64 0xFFFFFFFFFFFFFFF0UI64
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//
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// Define the location of the GART aperture control registers
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//
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//
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// The GART registers on the 440 live in the host-PCI bridge.
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// This is unfortunate, since the AGP driver attaches to the PCI-PCI (AGP)
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// bridge. So we have to get to the host-PCI bridge config space
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// and this is only possible because we KNOW this is bus 0, slot 0.
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//
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//
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// TBD: The GART registers on the 460 live in the GXB. Though we are trying to use
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// the code from 440 as much as possible. The HalGet calls may not be needed if
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// all the GART registers live on the PCI-PCI bridge (GXB). DOUBLE CHECK THIS
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// WITH THE EDS, VERIFY IT WITH JOHN VERT - NAGA G
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//
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// Compared to 440 there exists no equivalents for PAC configuration,
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// AGP Control & ATTBASE registers in 460GX.
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#define EXTRACT_LSBYTE(x) x = (x & 0xFF) // Sunil
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#define ONE_KB 1024
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#define ONE_MB (ONE_KB * ONE_KB)
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#define AP_256MB (256 * ONE_MB)
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#define AP_1GB (ONE_MB * ONE_KB)
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#define AP_32GB (32 * AP_1GB)
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#define ABOVE_TOM(x) ( (x) & (0x08) )
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#define AGP_460GX_IDENTIFIER 0x84E28086 // Device ID & Vendor ID
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// for the 460GX SAC
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#define APBASE_OFFSET 0x10 // Aperture Base Address:APBASE & BAPBASE are used to
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#define BAPBASE_OFFSET 0x98 // store the base address of the Graphics Aperture(GA).
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// Only one of APBASE or BAPBASE is visible at a time.
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// APBASE is visible when AGPSIZ[3]=0 && AGPSIZ[2:0]!=0.
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// BAPBASE is visible when AGPSIZ[3]=1 & AGPSIZ[2:0]!=0.
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// BAPBASE is used when the GA is mapped above 4GB and
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// APBASE when the GA is mapped below 4GB
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#define APSIZE_OFFSET 0xA2 // Aperture Size Register - AGPSIZ
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#define ATTBASE 0xFE200000 // Aperture Translation Table Base - It is a
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// 2MB region hard coded in 460GX to 0xFE200000h
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#define AGPSTATUS_OFFSET 0xE4 // AGP Status Register - The CAP_PTR is
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// at 0xE0h in 460GX and the AGP Status
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// register is at CAP_PTR+4.
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#define AGPCMD_OFFSET 0xE8 // AGP Command Register - CAP_PTR + 8
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//
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// 82460GX specific definitions to get to the PCI configuration space of the
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// SAC, GXB et al.
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//
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#define AGP460_SAC_BUS_ID 0 // The bus number where the SAC resides in 82460GX
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//
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// The following two definitions should be interpreted as of type PCI_SLOT_NUMBER
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// which combines the device & function number for a particular PCI device. It is
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// a ULONG value which should be deciphered as follows:
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// [xxxxxxxx xxxxxxxx xxxxxxxx YYYZZZZZ]
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// where x = Reserved, Y = Function Number, Z = Device Number
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//
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#define AGP460_SAC_CBN_SLOT_ID 0x10 // The Chipset Bus Number resides at Bus 0,
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// Device 10h & Function 0.
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#define AGP460_GXB_SLOT_ID 0x34 // The GXB would be accessed at Bus CBN, Device 14h
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// function BFN. BFN is 1 by default.
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#define AGP460_PAGE_SIZE_4KB (4 * ONE_KB)
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//
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// Handy macros to read & write in the PCI Configuration space
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//
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//
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// Read460CBN reads the CBN - Chipset Bus Number from the 82460GX SAC.
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// CBN is a BYTE located at Bus 0, Device 10h, Function 0, Offset 40
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// in the SAC Configuration space. The CBN can be read once and reused
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// subsequently.
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//
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void Read460CBN(PVOID CBN);
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void Read460Config(ULONG _CBN_,PVOID _buf_,ULONG _offset_,ULONG _size_);
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void Write460Config(ULONG _CBN_,PVOID _buf_,ULONG _offset_,ULONG _size_);
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//
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// Conversions from AGPSIZ[2:0] encoding to Aperture Size in MB/GB
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//
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// AGPSIZE[2:0] Aperture Size
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// 000 0MB (power on default; no GART SRAM present)
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// 001 256MB
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// 010 1GB
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// 100 32GB (only with 4MB pages)
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//
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#define AP_SIZE_0MB 0x00
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#define AP_SIZE_256MB 0x01
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#define AP_SIZE_1GB 0x02
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#define AP_SIZE_32GB 0x04
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#define AP_SIZE_COUNT_4KB 2 //Only apertures of 256M & 1G are possible with 4KB pages
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#define AP_SIZE_COUNT_4MB 3 //Apertures of 256M, 1G & 32G are possible with 4MB pages
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#define AP_MIN_SIZE AP_256MB // 0 is not counted as a possible
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// aperture size
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#define AP_MAX_SIZE_4KB AP_1GB // 1 GB is the maximum with 4KB pages
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#define AP_MAX_SIZE_4MB AP_1GB // 32GB is the maximum with 4MB pages
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#define PAGESIZE_460GX_CHIPSET (4 * ONE_KB)
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#define GART_PAGESHIFT_460GX 12
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//
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// Define the 82460GX GART table entry. 4KB pages are assumed. To support 4MB pages new
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// structures have to be defined.
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//
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typedef struct _GART_ENTRY_HW {
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ULONG Page : 24;
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ULONG Valid : 1;
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ULONG Coherency : 1;
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ULONG Parity : 1; // Parity bit is generated by Hardware. Software should
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// mask it out and treat it as a reserved.
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ULONG Reserved : 5;
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} GART_ENTRY_HW, *PGART_ENTRY_HW;
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//
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// GART Entry states are defined so that all software-only states
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// have the Valid bit clear.
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//
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#define GART_ENTRY_VALID 1 // Bit 24 is the valid bit in 460GX GART
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#define GART_ENTRY_FREE 0 // 000
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#define GART_ENTRY_WC 2 // 010
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#define GART_ENTRY_UC 4 // 100
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#define GART_ENTRY_WB 6 // 110
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#define GART_ENTRY_RESERVED_WC GART_ENTRY_WC
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#define GART_ENTRY_RESERVED_UC GART_ENTRY_UC
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#define GART_ENTRY_RESERVED_WB GART_ENTRY_WB
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//
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// Unlike 440, 82460GX GART driver doesn't have direct equivalent for GART PTE software
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// states like GART_ENTRY_VALID_WC, GART_ENTRY_VALID_UC etc. This is because of
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// the organization of the GART PTEs - the valid bit is disjoint from any reserved bits
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// and therefore have to be manipulated separately. - Naga G
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//
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typedef struct _GART_ENTRY_SW {
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ULONG Reserved0 : 24;
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ULONG Valid : 1;
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ULONG Reserved1 : 2;
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ULONG State : 3;
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ULONG Reserved2 : 2;
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} GART_ENTRY_SW, *PGART_ENTRY_SW;
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typedef struct _GART_PTE {
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union {
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GART_ENTRY_HW Hard;
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ULONG AsUlong;
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GART_ENTRY_SW Soft;
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};
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} GART_PTE, *PGART_PTE;
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//
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// Define the 460-specific extension
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//
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typedef struct _AGP460_EXTENSION {
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BOOLEAN GlobalEnable; // Software only bit. The GART will be
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// initialized to a known invalid state (0s)
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// during initialization. Other than that
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// no hardware control is available in 460GX
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// to enable/disable GART accesses. Thus, this
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// is not of much use !
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PHYSICAL_ADDRESS ApertureStart;
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ULONG ApertureLength; // Aperture Length in Bytes
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ULONG ChipsetPageSize; // Can be 4KB or 4MB.
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PGART_PTE Gart;
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ULONG GartLength; // Maximum is 2MB
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PHYSICAL_ADDRESS GartPhysical; // Physical address where GART starts
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BOOLEAN bSupportMultipleAGPDevices; // For future use.
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BOOLEAN bSupportsCacheCoherency; // For future use.
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ULONGLONG SpecialTarget;
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} AGP460_EXTENSION, *PAGP460_EXTENSION;
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NTSTATUS Agp460FlushPages(
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IN PAGP460_EXTENSION AgpContext,
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IN PMDL Mdl
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);
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