517 lines
17 KiB
C
517 lines
17 KiB
C
#ifndef CHECK_H_INCLUDED
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#define CHECK_H_INCLUDED
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//###########################################################################
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//**
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//** Copyright (C) 1996-99 Intel Corporation. All rights reserved.
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//**
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//** The information and source code contained herein is the exclusive
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//** property of Intel Corporation and may not be disclosed, examined
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//** or reproduced in whole or in part without explicit written authorization
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//** from the company.
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//**
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//###########################################################################
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//-----------------------------------------------------------------------------
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// Version control information follows.
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//
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// $Header: /dev/SAL/INCLUDE/check.h 3 4/21/00 12:52p Mganesan $
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// $Log: /dev/SAL/INCLUDE/check.h $
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//
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// 3 4/21/00 12:52p Mganesan
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// Sync Up SAL 5.8
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//
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// Rev 1.8 18 Jun 1999 16:29:00 smariset
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//
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//
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// Rev 1.7 08 Jun 1999 11:29:04 smariset
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//Added Fatal Error Define
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//
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// Rev 1.6 14 May 1999 09:01:26 smariset
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//removal of tabs
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//
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// Rev 1.5 07 May 1999 11:27:16 smariset
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//Copyright update and Platform Record Hdr. Update
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//
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// Rev 1.4 06 May 1999 16:06:42 smariset
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//PSI Record Valid Bits Change (No bnk Regs)
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//
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// Rev 1.3 05 May 1999 14:13:12 smariset
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//Pre Fresh Build
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//
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// Rev 1.2 24 Mar 1999 09:40:06 smariset
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//
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//
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// Rev 1.1 09 Mar 1999 13:12:52 smariset
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//updated
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//
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// Rev 1.0 09 Mar 1999 10:02:28 smariset
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//First time check
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//
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//*****************************************************************************//
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// #define _INTEL_CHECK_H 1
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#if defined(_INTEL_CHECK_H)
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#define OEM_RECID_CMOS_RAM_ADDR 64 // OEM should define this
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#define INIT_IPI_VECTOR 0x500
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// SAL_MC_SET_PARAMS
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#define RZ_VECTOR 0xf3
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#define WKP_VECTOR 0x12 // Rendz. wakeup interrupt vector (IA-32 MCHK Exception Vector)
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#define CMC_VECTOR 0xf2 //
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#define TIMEOUT 1000
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#endif // _INTEL_CHECK_H
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#define IntrVecType 0x01
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#define MemSemType 0x02
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#define RendzType 0x01
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#define WakeUpType 0x02
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#define CpevType 0x03
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// SAL_SET_VECTORS
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#define MchkEvent 0x00
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#define InitEvent 0x01
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#define BootRzEvent 0x02
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#if defined(_INTEL_CHECK_H)
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#define ProcCmcEvent 0x02
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#define PlatCmcEvent 0x03
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#define OsMcaSize 0x20
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#define OsInitSize 0x20
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// Misc. Flags
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#define OS_FLAG 0x03
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#define OEM_FLAG 0x04
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// Record Type
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#define PROC_RECORD 0x00
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#define PLAT_RECORD 0x01
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#define NUM_PROC 0x04 // number of processors
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#define PSI_REC_VERSION 0x01 // 0.01
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// Oem SubTypes
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#define MEM_Record 0x00
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#define BUS_Record 0x02
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#define COMP_Record 0x04
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#define SEL_Record 0x08
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// Record valid flags
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#define MEM_Record_VALID 0x00
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#define BUS_Record_VALID 0x02
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#define COMP_Record_VALID 0x04
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#define SEL_Record_VALID 0x08
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#define RdNvmRecord 0x00
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#define WrNvmRecord 0x01
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#define ClrNvmRecord 0x02
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#define ChkIfMoreNvmRecord 0x03
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#else // !_INTEL_CHECK_H
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// SAL 0800: Reserved 0x03-0x40
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// SAL STATE_INFO
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//
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// Thierry 08/2000 - WARNING:
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// These definitions match the ntos\inc\hal.h definitions for KERNEL_MCE_DELIVERY.Reserved.EVENTYPE.
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//
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#define MCA_EVENT 0x00 // MCA Event Information
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#define INIT_EVENT 0x01 // INIT Event Information
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#define CMC_EVENT 0x02 // Processor CMC Event Information
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#define CPE_EVENT 0x03 // Corrected Platform Event Information
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// SAL 0800: Reserved other values...
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#endif // !_INTEL_CHECK_H
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// // constant defines
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// Processor State Parameter error conditions from PAL in GR20
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// Processor State Parameters from PAL during machine check bit position
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#define PSPrz 2 // Rendez Request Success
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#define PSPra 3 // Rendez Attempted
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#define PSPme 4
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#define PSPmn 5
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#define PSPsy 6 // storage inetgrity
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#define PSPco 7 // continuable error
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#define PSPci 8 // contained error, recovery possible
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#define PSPus 9 // uncontained memory failure
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#define PSPhd 10 // damaged hardware
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#define PSPtl 11
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#define PSPmi 12
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#define PSPpi 13
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#define PSPpm 14
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#define PSPdy 15
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#define PSPin 16
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#define PSPrs 17
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#define PSPcm 18 // machine check corrected
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#define PSPex 19 // machine check expected
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#define PSPcr 20
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#define PSPpc 21
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#define PSPdr 22
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#define PSPtr 23
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#define PSPrr 24
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#define PSPar 25
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#define PSPbr 26
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#define PSPpr 27
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#define PSPfp 28
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#define PSPb1 29
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#define PSPb0 30
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#define PSPgr 31
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#define PSPcc 59 // cache check, SAL's domain
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#define PSPtc 60 // tlb check error, SAL's domain
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#define PSPbc 61 // bus check error, SAL's domain
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#define PSPrc 62 // register file check error, SAL's domain
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#define PSPuc 63 // unknown error, SAL's domain
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#define BusChktv 21 // Bus check.tv bit or bus error info
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#define CacheChktv 23
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#if defined(_INTEL_CHECK_H)
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// SAL PSI Validation flag bit mask
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#define vPSIpe 0x01<<0 // start bit pos. for processor error map
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#define vPSIps 0x01<<1
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#define vPSIid 0x01<<2 // processor LID register value
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#define vPSIStatic 0x01<<3 // processor static info.
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#define vPSIcc 0x01<<4 // start bit pos. for cache error
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#define vPSItc 0x01<<8 // start bit pos. for tlb errors
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#define vPSIbc 0x01<<12 // bus check valid bit
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#define vPSIrf 0x01<<16 // register file check valid bit
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#define vPSIms 0x01<<20 // ms check valid bit
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// Valid bit flags for CR and AR registers for this generation of EM Processor
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#define vPSIMinState 0x01<<0
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#define vPSIBRs 0x01<<1
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#define vPSICRs 0x01<<2
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#define vPSIARs 0x01<<3
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#define vPSIRRs 0x01<<4
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#define vPSIFRs 0x01<<5
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#define vPSIRegs vPSIBRs+vPSICRs+vPSIARs+vPSIRRs+vPSIMinState
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///*** All Processor PAL call specific info.
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// Processor Error Info Type Index for PAL_MC_ERROR_INFO call
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#define PROC_ERROR_MAP 0 // index for Proc. error map
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#define PROC_STATE_PARAM 1 // index for Proc. state parameter
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#define PROC_STRUCT 2 // index for structure specific error info.
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#define PEIsse 0 // index for Proc. structure specific level index
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#define PEIta 1 // index for target identifer
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#define PEIrq 2 // index for requestor
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#define PEIrs 3 // index for responder
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#define PEIip 4 // index for precise IP
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// processor error map starting bit positions for each field (level index)
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#define PEMcid 0 // core ID
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#define PEMtid 4 // thread ID
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#define PEMeic 8 // inst. cache error index
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#define PEMedc 12 // data cache error index
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#define PEMeit 16 // inst. tlb error index
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#define PEMedt 20 // data tlb error index
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#define PEMebh 24 // bus error index
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#define PEMerf 28 // register file error index
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#define PEMems 32 // micro-arch error index
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// processor structure specific error bit mappings
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#define PEtv 0x01<<60 // valid target identifier
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#define PErq 0x01<<61 // valid request identifier
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#define PErp 0x01<<62 // valid responder identifier
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#define PEpi 0x01<<63 // valid precise IP
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// Error Severity: using bits (cm) & (us) only
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#define RECOVERABLE 0x00
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#define FATAL 0x01
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#define CONTINUABLE 0x02
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#define BCib 0x05
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#define BCeb 0x06
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#else // !_INTEL_CHECK_H
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//
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// Error Severity: using vits (PSPcm) & (PSPus) only
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// The SAL spec'ed values are defined in ntos\inc\hal.h
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//
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// To remind you:
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// #define ErrorRecoverable ((USHORT)0)
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// #define ErrorFatal ((USHORT)1)
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// #define ErrorCorrected ((USHORT)2)
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//
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// The following values define some of the reserved ErrorOthers.
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#define ErrorBCeb ((USHORT)6)
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#endif // !_INTEL_CHECK_H
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#if defined(_INTEL_CHECK_H)
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// System Errors bits masks to be handled by SAL, mask bits in d64-d32
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#define parError 0x000100000000 // Memory parity error
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#define eccError 0x000200000000 // Memory ECC error
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#define busError PSPbc // System Bus Check/Error
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#define iocError 0x000800000000 // System IO Check Errors
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#define temError 0x002000000000 // System Temperature Error
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#define vccError 0x004000000000 // System Voltage Error
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#define intError 0x010000000000 // Intrusion Error for servers
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#define cacError PSPcc // Cache Error
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#define tlbError PSPtc // TLB error
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#define unkError PSPuc // Unknown/Catastrophic error
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// error bits masks
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#define PALErrMask 0x0ff // bit mask of errors correctable by PAL
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#define SALErrMask busError+cacError+tlbError+unkError // SAL error bit mask
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#define OSErrMask 0x0ff // OS expected error conditions
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#define MCAErrMask 0x0ff // Given MCA Error Mask bit map
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// New processor error Record structures ACO504
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typedef struct tagModInfo
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{
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U64 eValid; // Valid bits for module entries
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U64 eInfo; // error info cache/tlb/bus
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U64 ReqId; // requester ID
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U64 ResId; // responder ID
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U64 TarId; // target ID
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U64 IP; // Precise IP
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} ModInfo;
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typedef struct tagSAL_GUID
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{
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U32 Data1;
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U16 Data2;
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U16 Data3;
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U8 Data4[8];
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} SAL_GUID;
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typedef struct tagProcessorInfo
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{
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U64 ValidBits;
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U64 Pem; // processor map
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U64 Psp; // processor state parameter
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U64 Pid; // processor LID register value
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ModInfo cInfo[8]; // cache check max of 8
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ModInfo tInfo[8]; // tlb check max of 8
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ModInfo bInfo[4]; // bus check max or 4
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U64 rInfo[4]; // register file check max of 4
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U64 mInfo[4]; // micro-architectural information max of
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U64 Psi[584+8]; // 584 bytes
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} ProcessorInfo;
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typedef struct tagMinProcessorInfo
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{
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U64 ValidBits;
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U64 Psp; // processor state parameter
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U64 Pem; // processor map
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U64 Pid; // processor LID register value
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} MinProcessorInfo;
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// end ACO504 changes.
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// platform error Record structures
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typedef struct tagCfgSpace
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{
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// data - error register dump
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U64 CfgRegAddr; // register offset/addr
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U64 CfgRegVal; // register data/value
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} CfgSpace;
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typedef struct tagMemSpace
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{
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// data - error register dump
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U64 MemRegAddr; // register offset/addr
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U64 MemRegVal; // register data/value
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} MemSpace;
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typedef union tagMemCfgSpace
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{
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MemSpace mSpace;
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CfgSpace cSpace;
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} MemCfgSpace;
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typedef struct tagSysCompErr // per component
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{
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U64 vFlag; // bit63=PCI device Flag, LSB:valid bits for each field in the Record
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// header for component Record
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U64 BusNum; // bus number on which the component resides
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U64 DevNum; // same as device select
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U64 FuncNum; // function ID of the device
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U64 DevVenID; // PCI device & vendor ID
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U64 SegNum; // segment number as defined in SAL spec.
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// register dump info.
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U64 MemSpaceNumRegPair; // number of reg addr/value pairs returned in this Record
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U64 CfgSpaceNumRegPair; // number of reg addr/value pairs returned in this Record
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MemCfgSpace mcSpace; // register add/data value pair array
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} cErrRecord;
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#define BusNum_valid 0x01
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#define DevNum_valid 0x02
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#define FuncNum_valid 0x04
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#define DevVenID_valid 0x08
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#define SegNum_valid 0x10
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#define MemSpaceNumRegPair_valid 0x20
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#define CfgSpaceNumRegPair_valid 0x40
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#define mcSpace_valid 0x80
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typedef struct tagPlatErrSection
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{
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U64 vFlag; // valid bits for each type of Record
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U64 Addr; // memory address
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U64 Data; // memory data
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U64 CmdType; // command/operation type
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U64 BusID; // bus ID if applicable
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U64 RequesterID; // Requestor of the transaction if any
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U64 ResponderID; // Intended target or responder
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U64 NumOemExt; // Number of OEM Extension Arrays
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cErrRecord OemExt; // Value Array of OEM extensions
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} PlatformInfo;
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#define Addr_valid 0x01
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#define Data_valid 0x02
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#define CmdType_valid 0x04
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#define BusID_valid 0x08
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#define RequesterID_valid 0x10
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#define ResponderID_valid 0x20
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#define NumOemExt_valid 0x40
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#define OemExt_valid 0x80
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// over all Record structure (processor+platform)
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typedef union utagDeviceSpecificSection
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{
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ProcessorInfo procSection;
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PlatformInfo platSection;
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} DeviceSection;
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// SAL PSI Record & Section structure
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typedef struct tagPsiSectionHeader
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{
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SAL_GUID SectionGuid;
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U16 Revision;
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U16 Reserved;
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U32 SectionLength;
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} PsiSectionHeader;
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typedef struct tagPsiSection
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{
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SAL_GUID SectionGuid;
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U16 Revision;
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U16 Reserved;
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U32 SectionLength;
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DeviceSection DevSection;
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} PsiSection;
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typedef struct tagPsiRecordHeader
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{
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U64 RecordID;
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U16 Revision;
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U16 eSeverity;
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U32 RecordLength;
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U64 TimeStamp;
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} PsiRecordHeader;
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typedef struct tagPsiRecord
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{
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U64 RecordID;
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U16 Revision;
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U16 eSeverity;
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U32 RecordLength;
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U64 TimeStamp;
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PsiSection PsiDevSection;
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} PsiRecord;
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/*
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LION 460GX:
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SAC: SAC_FERR, SAC_FERR
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SDC: SDC_FERR, SDC_NERR
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MAC: FERR_MAC
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GXB: FERR_GXB, FERR_PCI, FERR_GART, FERR_F16, FERR_AGP
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*/
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typedef struct tagPciCfgHdr
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{
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U8 RegAddr;
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U8 FuncNum;
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U8 DevNum;
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U8 BusNum;
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U8 SegNum;
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U8 Res[3];
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} PciCfgHdr;
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#define PLATFORM_REC_CNT 0x01 // number of consecutive Records in the platform Record linked list
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#define OEM_EXT_REC_CNT 0x06 // number of consecutive OEM extension Array count
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// number of registers that will be returned for each device
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#define SAC_REG_CNT 0x02
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#define SDC_REG_CNT 0x02
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#define MAC_REG_CNT 0x01
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#define GXB_REG_CNT 0x04
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typedef struct tagSacRegs
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{
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PciCfgHdr pHdr;
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U64 RegCnt;
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U64 RegAddr[SAC_REG_CNT];
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} SacDevInfo;
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typedef struct tagSdcRegs
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{
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PciCfgHdr pHdr;
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U64 RegCnt;
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U64 RegAddr[SDC_REG_CNT];
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} SdcDevInfo;
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typedef struct tagMacRegs
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{
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PciCfgHdr pHdr;
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U64 RegCnt;
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U64 RegAddr[MAC_REG_CNT];
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} MacDevInfo;
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typedef struct tagGxbRegs
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{
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PciCfgHdr pHdr;
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U64 RegCnt;
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U64 RegAddr[GXB_REG_CNT];
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} GxbDevInfo;
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typedef struct tagDevInfo
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{
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PciCfgHdr pHdr;
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U64 RegCnt;
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U64 RegAddr[4];
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} DevInfo;
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#define DEV_VEN_ID_ADDR 0x0
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#define SAC_BN 0x10
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#define DevNumber0 0x0
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#define DevNumber1 0x1
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#define DevNumber2 0x2
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#define DevNumber3 0x3
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#define DevNumber4 0x4
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#define DevNumber5 0x5
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#define DevNumber6 0x6
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// function prototypes
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rArg _BuildProcErrSection(PsiRecord*, U64, U64, U64);
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rArg _BuildPlatErrSection(PsiSection*, U64, U64, U64);
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rArg _BuildChipSetSection(PsiSection*, U64);
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rArg _GetErrRecord(PsiRecord*, U64, PsiRecord*,PsiSection*, U64*, U64);
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rArg _NvmErrRecordMgr(U64, U64, U64, U64);
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rArg GetDeviceRecord(cErrRecord*, DevInfo*);
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rArg SAL_PCI_CONFIG_READ_(U64, U64, U64, U64, U64, U64, U64, U64);
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rArg SAL_PCI_CONFIG_WRITE_(U64, U64, U64, U64, U64, U64, U64, U64);
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rArg OemGetInitSource();
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rArg _MakeStaticPALCall(U64, U64, U64, U64, U64);
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rArg GetProcNum();
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#endif // _INTEL_CHECK_H
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#endif // CHECK_H_INCLUDED
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