1099 lines
28 KiB
NASM
1099 lines
28 KiB
NASM
title "Interval Clock Interrupt"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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; Copyright (c) 1992 Intel Corporation
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; All rights reserved
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;
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; INTEL CORPORATION PROPRIETARY INFORMATION
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;
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; This software is supplied to Microsoft under the terms
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; of a license agreement with Intel Corporation and may not be
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; copied nor disclosed except in accordance with the terms
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; of that agreement.
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;
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;
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; Module Name:
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;
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; mpclock.asm
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;
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; Abstract:
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;
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; This module implements the code necessary to field and process the
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; interval clock interrupt.
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;
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; Author:
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;
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; Shie-Lin Tzong (shielint) 12-Jan-1990
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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; Ron Mosgrove (Intel) Aug 1993
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; Modified to support PC+MP Systems
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;--
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.586p
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.xlist
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include hal386.inc
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include i386\ix8259.inc
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include i386\ixcmos.inc
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include callconv.inc
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include i386\kimacro.inc
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include mac386.inc
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include apic.inc
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include ntapic.inc
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include i386\mp8254.inc
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.list
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EXTRNP _KeUpdateSystemTime,0
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EXTRNP _KeUpdateRunTime,1,IMPORT
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EXTRNP Kei386EoiHelper,0,IMPORT
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EXTRNP _HalEndSystemInterrupt,2
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EXTRNP _HalBeginSystemInterrupt,3
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EXTRNP _HalpAcquireCmosSpinLock ,0
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EXTRNP _HalpReleaseCmosSpinLock ,0
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EXTRNP _HalpAcquireSystemHardwareSpinLock ,0
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EXTRNP _HalpReleaseSystemHardwareSpinLock ,0
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EXTRNP _HalpSetInitialClockRate,0
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EXTRNP _HalpMcaQueueDpc, 0
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EXTRNP _KeQueryPerformanceCounter, 1
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extrn _HalpRtcTimeIncrements:DWORD
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extrn _KdEnteredDebugger:DWORD
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extrn _HalpTimerWatchdogEnabled:DWORD
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extrn _HalpTimerWatchdogStorage:DWORD
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extrn _HalpTimerWatchdogCurFrame:DWORD
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extrn _HalpTimerWatchdogLastFrame:DWORD
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extrn _HalpTimerWatchdogStorageOverflow:DWORD
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ifdef ACPI_HAL
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ifdef NT_UP
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EXTRNP _HalpBrokenPiix4TimerTick, 0
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extrn _HalpBrokenAcpiTimer:byte
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endif
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endif
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ifdef MMTIMER
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EXTRNP _HalpmmTimerClockInterrupt, 0
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MMT_VECTOR EQU 0D3h
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endif
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;
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; Constants used to initialize CMOS/Real Time Clock
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;
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CMOS_CONTROL_PORT EQU 70h ; command port for cmos
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CMOS_DATA_PORT EQU 71h ; cmos data port
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CMOS_STATUS_BUSY EQU 80H ; Time update in progress
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D_INT032 EQU 8E00h ; access word for 386 ring 0 interrupt gate
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REGISTER_B_ENABLE_PERIODIC_INTERRUPT EQU 01000010B
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; RT/CMOS Register 'B' Init byte
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; Values for byte shown are
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; Bit 7 = Update inhibit
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; Bit 6 = Periodic interrupt enable
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; Bit 5 = Alarm interrupt disable
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; Bit 4 = Update interrupt disable
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; Bit 3 = Square wave disable
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; Bit 2 = BCD data format
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; Bit 1 = 24 hour time mode
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; Bit 0 = Daylight Savings disable
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REGISTER_B_DISABLE_PERIODIC_INTERRUPT EQU 00000010B
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;
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; RegisterAInitByte sets 8Hz clock rate, used during init to set up
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; KeStallExecutionProcessor, etc. (See RegASystemClockByte below.)
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;
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RegisterAInitByte EQU 00101101B ; RT/CMOS Register 'A' init byte
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; 32.768KHz Base divider rate
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; 8Hz int rate, period = 125.0ms
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PeriodInMicroSecond EQU 125000 ;
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COUNTER_TICKS_AVG_SHIFT EQU 4
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COUNTER_TICKS_FOR_AVG EQU 16
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PAGE_SIZE EQU 1000H
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FRAME_COPY_SIZE EQU 64
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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;
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; There is a "C" version of this structure in MPCLOCKC.C
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;
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TimeStrucSize EQU 20
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RtcTimeIncStruc struc
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RTCRegisterA dd 0 ;The RTC register A value for this rate
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RateIn100ns dd 0 ;This rate in multiples of 100ns
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RateAdjustmentNs dd 0 ;Error Correction (in ns)
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RateAdjustmentCnt dd 0 ;Error Correction (as a fraction of 256)
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IpiRate dd 0 ;IPI Rate Count (as a fraction of 256)
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RtcTimeIncStruc ends
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ifdef DBGSSF
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DebugSSFStruc struc
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SSFCount1 dd 0
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SSFCount2 dd 0
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SSFRdtsc1 dd 0
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SSFRdtsc2 dd 0
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SSFRdtsc3 dd 0
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SSFRna1 dd 0
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SSFRna2 dd 0
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SSFRna3 dd 0
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DebugSSFStruc ends
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public HalpDbgSSF
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HalpDbgSSF db (size DebugSSFStruc) * 10 dup (0)
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endif
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ALIGN dword
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public RTCClockFreq
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public RegisterAClockValue
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RTCClockFreq dd 156250
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RegisterAClockValue dd 00101010B ; default interval = 15.6250 ms
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MINIMUM_STALL_FACTOR EQU 10H ; Reasonable Minimum
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public HalpP0StallFactor
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HalpP0StallFactor dd MINIMUM_STALL_FACTOR
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public HalpInitStallComputedCount
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HalpInitStallComputedCount dd 0
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public HalpInitStallLoopCount
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HalpInitStallLoopCount dd 0
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ALIGN dword
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;
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; Clock Rate Adjustment Counter. This counter is used to keep a tally of
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; adjustments needed to be applied to the RTC rate as passed to the
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; kernel.
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;
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public _HalpCurrentRTCRegisterA, _HalpCurrentClockRateIn100ns
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public _HalpCurrentClockRateAdjustment, _HalpCurrentIpiRate
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public _HalpIpiRateCounter, _HalpNextMSRate, _HalpPendingRate
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public _HalpRateAdjustment
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_HalpCurrentRTCRegisterA dd 0
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_HalpCurrentClockRateIn100ns dd 0
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_HalpCurrentClockRateAdjustment dd 0
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_HalpCurrentIpiRate dd 0
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_HalpIpiRateCounter dd 0
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_HalpNextMSRate dd 0
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_HalpPendingRate dd 0
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_HalpRateAdjustment dd 0
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ifdef ACPI_HAL
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public _HalpCurrentMSRateTableIndex
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_HalpCurrentMSRateTableIndex dd 0
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endif
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;
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; HalpUse8254 - flag to indicate 8254 should be used
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; HalpSample8254 - count to sample 8254
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;
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; N.B. access to the 8254 is gaurded with the Cmos lock
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;
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public _HalpUse8254
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_HalpUse8254 db 0
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_HalpSample8254 db 0
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_b8254Reserved dw 0
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;
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; Flag to tell clock routine when P0 can Ipi Other processors
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;
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public _HalpIpiClock
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_HalpIpiClock dd 0
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public _HalpClockWork, _HalpClockSetMSRate, _HalpClockMcaQueueDpc
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_HalpClockWork label dword
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_HalpClockSetMSRate db 0
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_HalpClockMcaQueueDpc db 0
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_bReserved1 db 0
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_bReserved2 db 0
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;
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; timer latency watchdog variables
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;
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public _HalpWatchdogAvgCounter, _HalpWatchdogCountLow, _HalpWatchdogCountHigh
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public _HalpWatchdogTscLow, _HalpWatchdogTscHigh
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_HalpWatchdogAvgCounter dd 0
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_HalpWatchdogCountLow dd 0
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_HalpWatchdogCountHigh dd 0
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_HalpWatchdogTscLow dd 0
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_HalpWatchdogTscHigh dd 0
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_DATA ends
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PAGELK SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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page ,132
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subttl "Initialize Clock"
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;++
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;
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; VOID
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; HalpInitializeClock (
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; )
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;
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; Routine Description:
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;
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; This routine initialize system time clock using RTC to generate an
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; interrupt at every 15.6250 ms interval at APIC_CLOCK_VECTOR
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;
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; It also initializes the 8254 if the 8254 is to be used for performance
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; counters.
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;
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; See the definition of RegisterAClockValue if clock rate needs to be
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; changed.
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;
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; This routine assumes it runs during Phase 0 on P0.
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;
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; Arguments:
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;
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; None
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;
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; Return Value:
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;
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; None.
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;
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;--
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cPublicProc _HalpInitializeClock ,0
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;
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; timer latency watchdog initialization
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;
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cmp _HalpTimerWatchdogEnabled, 0
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jz short @f
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rdtsc
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mov _HalpWatchdogAvgCounter, COUNTER_TICKS_FOR_AVG
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mov _HalpWatchdogTscLow, eax
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mov _HalpWatchdogTscHigh, edx
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xor eax, eax
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mov _HalpWatchdogCountLow, eax
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mov _HalpWatchdogCountHigh, eax
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@@:
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pushfd ; save caller's eflag
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cli ; make sure interrupts are disabled
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stdCall _HalpSetInitialClockRate
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;
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; Set the interrupt rate to what is actually needed
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;
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stdCall _HalpAcquireCmosSpinLock ; intr disabled
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mov eax, _HalpCurrentRTCRegisterA
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shl ax, 8
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mov al, 0AH ; Register A
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CMOS_WRITE ; Initialize it
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;
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; Don't clobber the Daylight Savings Time bit in register B, because we
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; stash the LastKnownGood "environment variable" there.
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;
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mov ax, 0bh
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CMOS_READ
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and al, 1
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mov ah, al
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or ah, REGISTER_B_ENABLE_PERIODIC_INTERRUPT
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mov al, 0bh
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CMOS_WRITE ; Initialize it
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mov al,0CH ; Register C
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CMOS_READ ; Read to initialize
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mov al,0DH ; Register D
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CMOS_READ ; Read to initialize
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stdCall _HalpReleaseCmosSpinLock
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;
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; For HALAACPI (free), init the 8254 so we can use it to
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; verify the ACPI timer frequency
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;
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ifdef ACPI_HAL
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ifdef NT_UP
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jmp short Hic50
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endif
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endif
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cmp _HalpUse8254, 0
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jz short Hic90
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Hic50:
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stdCall _HalpAcquireSystemHardwareSpinLock ; intr disabled
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; Program 8254 to count down the maximum interval
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; (8254 access is gaurded with CmosSpinLock)
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mov eax, PERFORMANCE_INTERVAL
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mov ecx, eax
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; set up counter 0 for periodic, binary count-down from max value
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mov al,COMMAND_8254_COUNTER0+COMMAND_8254_RW_16BIT+COMMAND_8254_MODE2
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out TIMER1_CONTROL_PORT0, al ; program count mode of timer 0
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IoDelay
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mov al, cl
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out TIMER1_DATA_PORT0, al ; program counter 0 LSB count
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IoDelay
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mov al,ch
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out TIMER1_DATA_PORT0, al ; program counter 0 MSB count
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or _HalpUse8254, PERF_8254_INITIALIZED
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stdCall _HalpReleaseSystemHardwareSpinLock
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Hic90:
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popfd ; restore caller's eflag
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stdRET _HalpInitializeClock
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stdENDP _HalpInitializeClock
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PAGELK ends
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_TEXT SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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page ,132
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subttl "System Clock Interrupt"
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;++
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;
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; Routine Description:
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;
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;
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; This routine is entered as the result of an interrupt generated by CLOCK2.
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; Its function is to dismiss the interrupt, raise system Irql to
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; CLOCK2_LEVEL, update performance counter and transfer control to the
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; standard system routine to update the system time and the execution
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; time of the current thread
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; and process.
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;
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;
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; Arguments:
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;
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; None
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; Interrupt is disabled
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;
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; Return Value:
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;
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; Does not return, jumps directly to KeUpdateSystemTime, which returns
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;
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; Sets Irql = CLOCK2_LEVEL and dismisses the interrupt
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;
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;--
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APIC_ICR_CLOCK equ (DELIVER_FIXED OR ICR_ALL_EXCL_SELF OR APIC_CLOCK_VECTOR)
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ENTER_DR_ASSIST Hci_a, Hci_t
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cPublicProc _HalpClockInterrupt ,0
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;
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; Save machine state in trap frame
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;
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ENTER_INTERRUPT Hci_a, Hci_t
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;
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; (esp) - base of trap frame
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;
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; dismiss interrupt and raise Irql
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;
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push APIC_CLOCK_VECTOR
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sub esp, 4 ; allocate space to save OldIrql
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stdCall _HalBeginSystemInterrupt, <CLOCK2_LEVEL,APIC_CLOCK_VECTOR,esp>
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ifdef NT_UP
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ifdef ACPI_HAL
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;
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; Check to see if we need to fix up a broken PIIX4
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;
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.if (_HalpBrokenAcpiTimer)
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stdCall _HalpBrokenPiix4TimerTick
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.endif
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endif
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endif
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mov al, _HalpUse8254
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or al, al
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jz short Hci90
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add _HalpSample8254, 56h
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jnc short Hci90
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; Call KeQueryPerformanceCounter() so that wrap-around of 8254 is
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; detected and the base value for performance counters updated.
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; Ignore returned value and reset HalpSample8254.
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;
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; WARNING - change increment value above if maximum RTC time increment
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; is increased to be more than current maximum value of 15.625 ms.
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; Currently the call will be made every 3rd timer tick.
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xor eax, eax
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mov _HalpSample8254, al
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stdCall _KeQueryPerformanceCounter, <eax>
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Hci90:
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;
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; This is the RTC interrupt, so we have to clear the
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; interrupt flag on the RTC.
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;
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stdCall _HalpAcquireCmosSpinLock
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;
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; clear interrupt flag on RTC by banging on the CMOS. On some systems this
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; doesn't work the first time we do it, so we do it twice. It is rumored that
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; some machines require more than this, but that hasn't been observed with NT.
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;
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mov al,0CH ; Register C
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CMOS_READ ; Read to initialize
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mov al,0CH ; Register C
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CMOS_READ ; Read to initialize
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stdCall _HalpReleaseCmosSpinLock
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mov eax, _HalpCurrentClockRateIn100ns
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xor ebx, ebx
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;
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; Adjust the tick count as needed
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;
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mov ecx, _HalpCurrentClockRateAdjustment
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add byte ptr _HalpRateAdjustment, cl
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sbb eax, ebx
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;
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; (esp) = OldIrql
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; (esp+4) = Vector
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; (esp+8) = base of trap frame
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; eax = time increment of this tick
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; ebx = 0
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;
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;
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; With an APIC Based System we will force a clock interrupt to all other
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; processors. This is not really an IPI in the NT sense of the word, it
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; uses the Local Apic to generate interrupts to other CPU's.
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;
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ifdef NT_UP
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; UP implemention, we don't care about IPI's here
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else ; ! NT_UP
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;
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; See if we need to IPI anyone, this happens only at the
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; Lowest supported frequency (ie the value KeSetTimeIncrement
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; is called with. We have a IPI Rate based upon the current
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; clock rate relative to the lowest clock rate.
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;
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mov ecx, _HalpIpiRateCounter
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add ecx, _HalpCurrentIpiRate
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cmp ch, bl
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mov byte ptr _HalpIpiRateCounter, cl
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jz short HalpDontSendClockIpi ; No, Skip it
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;
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; Don't send vectors onto the APIC bus until at least one other
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; processor comes on line. Vectors placed on the bus will hang
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; around until someone picks them up.
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;
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cmp _HalpIpiClock, ebx
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je short HalpDontSendClockIpi
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;
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; At least one other processor is alive, send clock pulse to all
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; other processors
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;
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; We use a destination shorthand and therefore only needs to
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; write the lower 32 bits of the ICR.
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pushfd
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cli
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;
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; Now issue the Clock IPI Command by writing to the Memory Mapped Register
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;
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STALL_WHILE_APIC_BUSY
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mov dword ptr APIC[LU_INT_CMD_LOW], APIC_ICR_CLOCK
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popfd
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HalpDontSendClockIpi:
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endif ; NT_UP
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cmp dword ptr _HalpTimerWatchdogEnabled, 0
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jz Hci15
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push eax
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;
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; Timer latency watchdog code
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;
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rdtsc
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;
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; Compare difference to watchdog count, while storing a copy of the
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; current counter.
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;
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push eax
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push edx
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sub eax, _HalpWatchdogTscLow
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sbb edx, _HalpWatchdogTscHigh
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pop _HalpWatchdogTscHigh
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pop _HalpWatchdogTscLow
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js Hci115 ; Was this a bogus counter?
|
|
; (e.g, negative delta)
|
|
|
|
push eax
|
|
push edx
|
|
mov ecx, dword ptr _KdEnteredDebugger
|
|
mov eax, [ecx] ; eax =
|
|
xor edx, edx ; InterlockedExchange(
|
|
@@: cmpxchg [ecx], edx ; &KdEnteredDebugger,
|
|
jnz short @b ; TRUE );
|
|
or al, al
|
|
pop edx
|
|
pop eax
|
|
jnz Hci14 ; In the debugger? Yes, skip it.
|
|
|
|
cmp _HalpPendingRate, ebx ; Was a new rate set during last
|
|
jnz Hci14 ; tick? Yes, skip this compare
|
|
|
|
;
|
|
; If we need to compute the average of the time-stamp counter for
|
|
; the current period, add the delta to the counter.
|
|
;
|
|
|
|
cmp _HalpWatchdogAvgCounter, ebx
|
|
jnz Hci12
|
|
|
|
cmp edx, _HalpWatchdogCountHigh
|
|
ja short Hci11
|
|
jb Hci14
|
|
|
|
cmp eax, _HalpWatchdogCountLow
|
|
jbe Hci14
|
|
|
|
Hci11:
|
|
cmp dword ptr [_HalpTimerWatchdogCurFrame], 0
|
|
je short Hci115
|
|
cmp dword ptr [_HalpTimerWatchdogStorageOverflow], 0
|
|
jne short Hci115
|
|
|
|
;
|
|
; copy FRAME_COPY_SIZE dwords from the stack, or to next page boundary,
|
|
; whichever is less
|
|
;
|
|
|
|
push esi
|
|
push edi
|
|
lea esi, [esp+8]
|
|
lea ecx, [esi + PAGE_SIZE - 1]
|
|
and ecx, NOT(PAGE_SIZE - 1)
|
|
sub ecx, esi
|
|
shr ecx, 2
|
|
cmp ecx, FRAME_COPY_SIZE
|
|
jbe short Hci112
|
|
mov ecx, FRAME_COPY_SIZE
|
|
Hci111:
|
|
mov edi, dword ptr _HalpTimerWatchdogCurFrame
|
|
rep movsd
|
|
add _HalpTimerWatchdogCurFrame, (FRAME_COPY_SIZE*4)
|
|
;
|
|
; If we didn't copy an entire FRAME_COPY_SIZE dwords, zero fill.
|
|
;
|
|
mov ecx, dword ptr _HalpTimerWatchdogCurFrame
|
|
sub ecx, edi
|
|
shr ecx, 2
|
|
xor eax, eax
|
|
rep stosd
|
|
cmp edi, dword ptr _HalpTimerWatchdogLastFrame
|
|
jbe short Hci112
|
|
mov dword ptr [_HalpTimerWatchdogStorageOverflow], 1
|
|
Hci112:
|
|
|
|
pop edi
|
|
pop esi
|
|
|
|
Hci115:
|
|
|
|
;
|
|
; Reset last time so that we're accurate after the trap
|
|
;
|
|
rdtsc
|
|
mov _HalpWatchdogTscHigh, edx
|
|
mov _HalpWatchdogTscLow, eax
|
|
|
|
jmp short Hci14
|
|
|
|
Hci12:
|
|
;
|
|
; Increment the total counter, perform average when the count is reached
|
|
;
|
|
|
|
add _HalpWatchdogCountLow, eax
|
|
adc _HalpWatchdogCountHigh, edx
|
|
dec _HalpWatchdogAvgCounter
|
|
jnz short Hci14
|
|
|
|
mov edx, _HalpWatchdogCountHigh
|
|
mov eax, _HalpWatchdogCountLow
|
|
|
|
;
|
|
; compute the average * 2, this measures when we have missed
|
|
; an interrupt at this rate.
|
|
;
|
|
mov ecx, COUNTER_TICKS_AVG_SHIFT - 1
|
|
Hci13:
|
|
shr edx, 1
|
|
rcr eax, 1
|
|
loop short Hci13
|
|
|
|
mov _HalpWatchdogCountLow, eax
|
|
mov _HalpWatchdogCountHigh, edx
|
|
|
|
Hci14:
|
|
pop eax
|
|
|
|
Hci15:
|
|
;
|
|
; Check for any more work
|
|
;
|
|
cmp _HalpClockWork, ebx ; Any clock interrupt work desired?
|
|
jz _KeUpdateSystemTime@0 ; No, process tick
|
|
|
|
cmp _HalpClockMcaQueueDpc, bl
|
|
je short CheckTimerRate
|
|
|
|
mov _HalpClockMcaQueueDpc, bl
|
|
|
|
;
|
|
; Queue MCA Dpc
|
|
;
|
|
|
|
push eax
|
|
stdCall _HalpMcaQueueDpc ; Queue MCA Dpc
|
|
pop eax
|
|
|
|
CheckTimerRate:
|
|
;
|
|
; (esp) = OldIrql
|
|
; (esp+4) = Vector
|
|
; (esp+8) = base of trap frame
|
|
; ebp = trap frame
|
|
; eax = time increment of this tick
|
|
; ebx = 0
|
|
;
|
|
cmp _HalpClockSetMSRate, bl ; New clock rate desired?
|
|
jz _KeUpdateSystemTime@0 ; No, process tick
|
|
|
|
|
|
;
|
|
; Time of clock frequency is being changed. See if we have changed rates
|
|
; since the last tick
|
|
;
|
|
cmp _HalpPendingRate, ebx ; Was a new rate set durning last
|
|
jnz SetUpForNextTick ; tick? Yes, go update globals
|
|
|
|
ProgramTimerRate:
|
|
|
|
; (eax) = time increment for current tick
|
|
|
|
;
|
|
; A new clock rate needs to be set. Setting the rate here will
|
|
; cause the tick after the next tick to be at the new rate.
|
|
; (the next tick is already in progress and will occur at the same
|
|
; rate as this tick)
|
|
;
|
|
|
|
push eax
|
|
|
|
stdCall _HalpAcquireCmosSpinLock
|
|
|
|
mov eax, _HalpNextMSRate
|
|
mov _HalpPendingRate, eax ; pending rate
|
|
|
|
dec eax
|
|
mov ecx, TimeStrucSize
|
|
xor edx, edx
|
|
mul ecx
|
|
|
|
mov eax, _HalpRtcTimeIncrements[eax].RTCRegisterA
|
|
mov _HalpCurrentRTCRegisterA, eax
|
|
|
|
shl ax, 8 ; (ah) = (al)
|
|
mov al, 0AH ; Register A
|
|
CMOS_WRITE ; Set it
|
|
|
|
cmp _HalpTimerWatchdogEnabled, 0
|
|
jz short @f
|
|
;
|
|
; Timer latency watchdog: schedule to recalibrate TSC delta
|
|
;
|
|
rdtsc
|
|
mov _HalpWatchdogAvgCounter, COUNTER_TICKS_FOR_AVG
|
|
mov _HalpWatchdogTscLow, eax
|
|
mov _HalpWatchdogTscHigh, edx
|
|
|
|
xor eax,eax
|
|
mov _HalpWatchdogCountHigh, eax
|
|
mov _HalpWatchdogCountLow, eax
|
|
@@:
|
|
|
|
stdCall _HalpReleaseCmosSpinLock
|
|
|
|
pop eax
|
|
jmp _KeUpdateSystemTime@0 ; dispatch this tick
|
|
|
|
SetUpForNextTick:
|
|
|
|
;
|
|
; The next tick will occur at the rate which was programmed during the last
|
|
; tick. Update globals for new rate which starts with the next tick.
|
|
;
|
|
; We will get here if there is a request for a rate change. There could
|
|
; been two requests. That is why we are conmparing the Pending with the
|
|
; NextRate.
|
|
;
|
|
; (eax) = time increment for current tick
|
|
;
|
|
push eax
|
|
|
|
mov eax, _HalpPendingRate
|
|
dec eax
|
|
|
|
ifdef ACPI_HAL
|
|
ifdef NT_UP
|
|
;
|
|
; Update the index used by Piix4 workaround; this maps RTC system clock
|
|
; milisecond indices into PM Timer (PMT) milisecond indices
|
|
;
|
|
; RTC { 0=1ms, 1=2ms, 2=4ms, 3=8ms, 4=15.6ms }
|
|
;
|
|
; PMT { 0=1ms, 1=2ms, 2=3ms, ..., 14=15ms }
|
|
;
|
|
; So to convert from RTC index to PMT: PMT = (1 << RTC) - 1
|
|
;
|
|
; NOTE: Since the PM timer array only goes to 15ms, we map our last RTC
|
|
; index (4=15.6) to PMT index 14 (15ms) as a special case
|
|
;
|
|
mov edx, 1
|
|
mov cl, al
|
|
shl edx, cl
|
|
dec edx
|
|
cmp edx, 0fh ; Check for special case RTC 15.6ms -> PMT 15ms
|
|
jne short @f
|
|
dec edx
|
|
|
|
@@:
|
|
mov _HalpCurrentMSRateTableIndex, edx
|
|
endif
|
|
endif
|
|
|
|
mov ecx, TimeStrucSize
|
|
xor edx, edx
|
|
mul ecx
|
|
|
|
mov ebx, _HalpRtcTimeIncrements[eax].RateIn100ns
|
|
mov ecx, _HalpRtcTimeIncrements[eax].RateAdjustmentCnt
|
|
mov edx, _HalpRtcTimeIncrements[eax].IpiRate
|
|
mov _HalpCurrentClockRateIn100ns, ebx
|
|
mov _HalpCurrentClockRateAdjustment, ecx
|
|
mov _HalpCurrentIpiRate, edx
|
|
|
|
mov ebx, _HalpPendingRate
|
|
mov _HalpPendingRate, 0 ; no longer pending, clear it
|
|
|
|
pop eax
|
|
|
|
cmp ebx, _HalpNextMSRate ; new rate == NextRate?
|
|
jne ProgramTimerRate ; no, go set new pending rate
|
|
|
|
mov _HalpClockSetMSRate, 0 ; all done setting new rate
|
|
jmp _KeUpdateSystemTime@0 ; dispatch this tick
|
|
|
|
|
|
stdENDP _HalpClockInterrupt
|
|
|
|
page ,132
|
|
subttl "System Clock Interrupt - Non BSP"
|
|
;++
|
|
;
|
|
; Routine Description:
|
|
;
|
|
;
|
|
; This routine is entered as the result of an interrupt generated by
|
|
; CLOCK2. Its function is to dismiss the interrupt, raise system Irql
|
|
; to CLOCK2_LEVEL, transfer control to the standard system routine to
|
|
; the execution time of the current thread and process.
|
|
;
|
|
; This routine is executed on all processors other than P0
|
|
;
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None
|
|
; Interrupt is disabled
|
|
;
|
|
; Return Value:
|
|
;
|
|
; Does not return, jumps directly to KeUpdateSystemTime, which returns
|
|
;
|
|
; Sets Irql = CLOCK2_LEVEL and dismisses the interrupt
|
|
;
|
|
;--
|
|
|
|
ENTER_DR_ASSIST HPn_a, HPn_t
|
|
|
|
cPublicProc _HalpClockInterruptPn ,0
|
|
|
|
;
|
|
; Save machine state in trap frame
|
|
;
|
|
|
|
ENTER_INTERRUPT HPn_a, HPn_t
|
|
|
|
;
|
|
; (esp) - base of trap frame
|
|
;
|
|
; dismiss interrupt and raise Irql
|
|
;
|
|
|
|
push APIC_CLOCK_VECTOR
|
|
sub esp, 4 ; allocate space to save OldIrql
|
|
stdCall _HalBeginSystemInterrupt, <CLOCK2_LEVEL,APIC_CLOCK_VECTOR,esp>
|
|
|
|
;
|
|
; All processors will update RunTime for current thread
|
|
;
|
|
|
|
sti
|
|
; TOS const PreviousIrql
|
|
stdCall _KeUpdateRunTime,<dword ptr [esp]>
|
|
|
|
INTERRUPT_EXIT ; lower irql to old value, iret
|
|
|
|
;
|
|
; We don't return here
|
|
;
|
|
|
|
stdENDP _HalpClockInterruptPn
|
|
|
|
|
|
page ,132
|
|
subttl "System Clock Interrupt - Stub"
|
|
;++
|
|
;
|
|
; Routine Description:
|
|
;
|
|
;
|
|
; This routine is entered as the result of an interrupt generated by
|
|
; CLOCK2. Its function is to interrupt and return.
|
|
;
|
|
; This routine is executed on P0 During Phase 0
|
|
;
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None
|
|
; Interrupt is disabled
|
|
;
|
|
; Return Value:
|
|
;
|
|
;--
|
|
|
|
APIC_ICR_CLOCK equ (DELIVER_FIXED OR ICR_ALL_EXCL_SELF OR APIC_CLOCK_VECTOR)
|
|
|
|
ENTER_DR_ASSIST HStub_a, HStub_t
|
|
|
|
cPublicProc _HalpClockInterruptStub ,0
|
|
|
|
;
|
|
; Save machine state in trap frame
|
|
;
|
|
|
|
ENTER_INTERRUPT HStub_a, HStub_t
|
|
|
|
;
|
|
; (esp) - base of trap frame
|
|
;
|
|
|
|
;
|
|
; clear interrupt flag on RTC by banging on the CMOS. On some systems this
|
|
; doesn't work the first time we do it, so we do it twice. It is rumored that
|
|
; some machines require more than this, but that hasn't been observed with NT.
|
|
;
|
|
|
|
mov al,0CH ; Register C
|
|
CMOS_READ ; Read to initialize
|
|
mov al,0CH ; Register C
|
|
CMOS_READ ; Read to initialize
|
|
|
|
Hpi10: test al, 80h
|
|
jz short Hpi15
|
|
mov al,0CH ; Register C
|
|
CMOS_READ ; Read to initialize
|
|
jmp short Hpi10
|
|
Hpi15:
|
|
|
|
mov dword ptr APIC[LU_EOI], 0 ; send EOI to APIC local unit
|
|
|
|
;
|
|
; Do interrupt exit processing without EOI
|
|
;
|
|
|
|
SPURIOUS_INTERRUPT_EXIT
|
|
|
|
;
|
|
; We don't return here
|
|
;
|
|
|
|
stdENDP _HalpClockInterruptStub
|
|
|
|
ifdef MMTIMER
|
|
page ,132
|
|
subttl "Multi Media Event Timer System Clock Interrupt Stub"
|
|
;++
|
|
;
|
|
; Routine Description:
|
|
;
|
|
;
|
|
; This routine is entered as the result of an interrupt generated by
|
|
; CLOCK2, its function is to interrupt, call HalpmmTimerClockInterrupt
|
|
; to update performance counters and adjust the system clock frequency
|
|
; if necessary, to IPI other processors, and update system time
|
|
;
|
|
; This routine is executed on P0
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None - Interrupt is disabled
|
|
;
|
|
; Return Value:
|
|
;
|
|
;--
|
|
|
|
ENTER_DR_ASSIST Hmmt_a, Hmmt_t
|
|
|
|
cPublicProc _HalpmmTimerClockInterruptStub
|
|
|
|
;
|
|
; Save machine state in trap frame
|
|
;
|
|
|
|
ENTER_INTERRUPT Hmmt_a, Hmmt_t
|
|
|
|
;
|
|
; (esp) - base of trap frame
|
|
;
|
|
; dismiss interrupt and raise Irql
|
|
;
|
|
|
|
push MMT_VECTOR
|
|
sub esp, 4 ; allocate space to save OldIrql
|
|
stdCall _HalBeginSystemInterrupt, <CLOCK2_LEVEL,MMT_VECTOR,esp>
|
|
|
|
;
|
|
; Update performace counter and adjust clock frequency if necessary
|
|
;
|
|
|
|
stdCall _HalpmmTimerClockInterrupt
|
|
|
|
INTERRUPT_EXIT ; lower irql to old value, iret
|
|
|
|
;
|
|
; We don't return here
|
|
;
|
|
|
|
stdENDP _HalpmmTimerClockInterruptStub
|
|
endif
|
|
|
|
ifdef ACPI_HAL
|
|
page ,132
|
|
subttl "Query 8254 Counter"
|
|
;++
|
|
;
|
|
; ULONG
|
|
; HalpQuery8254Counter(
|
|
; VOID
|
|
; )
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; This routine returns the current value of the 8254 counter
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None
|
|
;
|
|
; Return Value:
|
|
;
|
|
; Current value of the 8254 counter is returned
|
|
;
|
|
;--
|
|
|
|
cPublicProc _HalpQuery8254Counter, 0
|
|
|
|
stdCall _HalpAcquireSystemHardwareSpinLock ; intr disabled
|
|
|
|
;
|
|
; Fetch the current counter value from the hardware
|
|
;
|
|
|
|
mov al, COMMAND_8254_LATCH_READ + COMMAND_8254_COUNTER0
|
|
; Latch PIT Ctr 0 command.
|
|
out TIMER1_CONTROL_PORT0, al
|
|
IODelay
|
|
in al, TIMER1_DATA_PORT0 ; Read PIT Ctr 0, LSByte.
|
|
IODelay
|
|
movzx ecx, al ; Zero upper bytes of (ECX).
|
|
in al, TIMER1_DATA_PORT0 ; Read PIT Ctr 0, MSByte.
|
|
mov ch, al ; (CX) = PIT Ctr 0 count.
|
|
|
|
mov eax, ecx
|
|
|
|
stdCall _HalpReleaseSystemHardwareSpinLock
|
|
|
|
stdRET _HalpQuery8254Counter
|
|
|
|
stdENDP _HalpQuery8254Counter
|
|
endif
|
|
|
|
_TEXT ends
|
|
|
|
end
|