363 lines
9.3 KiB
C
363 lines
9.3 KiB
C
/*++
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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ixdat.c
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Abstract:
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Declares various data which is initialize data, or pagable data.
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Author:
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "halp.h"
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#include "apic.inc"
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#include "pci.h"
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#include "pcip.h"
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#include "pcmp_nt.inc"
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#include "ixsleep.h"
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#ifdef ALLOC_DATA_PRAGMA
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#pragma data_seg("INIT")
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#endif
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//
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// The following data is only valid during system initialiation
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// and the memory will be re-claimed by the system afterwards
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//
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ADDRESS_USAGE HalpDefaultPcIoSpace = {
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NULL, CmResourceTypePort, InternalUsage,
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{
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#ifndef MCA
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0x000, 0x10, // ISA DMA
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0x0C0, 0x10, // ISA DMA
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#else
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0x000, 0x20, // MCA DMA
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0x0C0, 0x20, // MCA DMA
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#endif
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0x080, 0x10, // DMA
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0x020, 0x2, // PIC
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0x0A0, 0x2, // Cascaded PIC
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0x040, 0x4, // Timer1, Referesh, Speaker, Control Word
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0x048, 0x4, // Timer2, Failsafe
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#if 0 // HACKHACK Remove for now since Intelille mouse software claims it.
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0x061, 0x1, // NMI (system control port B)
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#endif
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0x092, 0x1, // system control port A
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0x070, 0x2, // Cmos/NMI enable
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#ifdef MCA
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0x074, 0x3, // Extended CMOS
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0x090, 0x2, // Arbritration Control Port, Card Select Feedback
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0x093, 0x2, // Reserved, System board setup
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0x096, 0x2, // POS channel select
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#endif
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0x0F0, 0x10, // coprocessor ports
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0xCF8, 0x8, // PCI Config Space Access Pair
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0,0
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}
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};
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ADDRESS_USAGE HalpEisaIoSpace = {
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NULL, CmResourceTypePort, InternalUsage,
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{
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0x0D0, 0x10, // DMA
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0x400, 0x10, // DMA
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0x480, 0x10, // DMA
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0x4C2, 0xE, // DMA
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0x4D4, 0x2C, // DMA
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0x461, 0x2, // Extended NMI
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0x464, 0x2, // Last Eisa Bus Muster granted
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0x4D0, 0x2, // edge/level control registers
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0xC84, 0x1, // System board enable
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0, 0
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}
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};
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#ifndef ACPI_HAL
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ADDRESS_USAGE HalpDetectedROM = {
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NULL,
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CmResourceTypeMemory,
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InternalUsage | RomResource,
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{
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0,0, // 32 ROM blocks, get initialized in ixusage.c
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0,
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0,0
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}
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};
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#endif
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ADDRESS_USAGE HalpImcrIoSpace = {
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NULL, CmResourceTypeMemory, InternalUsage,
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{
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0x022, 0x02, // ICMR ports
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0, 0
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}
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};
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//
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// From usage.c
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//
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WCHAR HalpSzSystem[] = L"\\Registry\\Machine\\Hardware\\Description\\System";
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WCHAR HalpSzSerialNumber[] = L"Serial Number";
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ADDRESS_USAGE *HalpAddressUsageList = NULL;
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//
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// From ixpcibus.c
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//
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WCHAR rgzMultiFunctionAdapter[] = L"\\Registry\\Machine\\Hardware\\Description\\System\\MultifunctionAdapter";
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WCHAR rgzConfigurationData[] = L"Configuration Data";
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WCHAR rgzIdentifier[] = L"Identifier";
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WCHAR rgzPCIIdentifier[] = L"PCI";
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WCHAR rgzPCICardList[] = L"\\Registry\\Machine\\System\\CurrentControlSet\\Control\\PnP\\PCI\\CardList";
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//
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// From ixpcibrd.c
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//
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WCHAR rgzReservedResources[] = L"\\Registry\\Machine\\System\\CurrentControlSet\\Control\\SystemResources\\ReservedResources";
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//
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// From ixinfo.c
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//
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WCHAR rgzSuspendCallbackName[] = L"\\Callback\\SuspendHibernateSystem";
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//
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// Strings used for boot.ini options
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// from mphal.c
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//
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UCHAR HalpSzBreak[] = "BREAK";
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UCHAR HalpSzOneCpu[] = "ONECPU";
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UCHAR HalpSzPciLock[] = "PCILOCK";
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UCHAR HalpSzTimerRes[] = "TIMERES";
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UCHAR HalpGenuineIntel[]= "GenuineIntel";
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UCHAR HalpSzClockLevel[]= "CLKLVL";
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UCHAR HalpSzUse8254[] = "USE8254";
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UCHAR HalpSzInterruptAffinity[]= "INTAFFINITY";
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UCHAR HalpSzForceClusterMode[]= "MAXPROCSPERCLUSTER";
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//
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// From ixcmos.asm
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//
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UCHAR HalpSerialLen = 0;
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UCHAR HalpSerialNumber[31] = {0};
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//
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// Copy of floating structure
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// from detection code
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//
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struct FloatPtrStruct HalpFloatStruct;
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UCHAR rgzBadHal[] = "\n\n" \
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"HAL: This HAL.DLL requires an MPS version 1.1 system\n" \
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"Replace HAL.DLL with the correct hal for this system\n" \
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"The system is halting";
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UCHAR rgzRTCNotFound[] = "HAL: No RTC device interrupt\n";
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//
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// Table to translate PCMP BusType to NT INTERFACE_TYPEs
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// All Eisa, Isa, VL buses are squashed onto one space
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// from mpsys.c
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//
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NTSTATUS
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HalpAddEisaBus (
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PBUS_HANDLER Bus
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);
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NTSTATUS
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HalpAddPciBus (
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PBUS_HANDLER Bus
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);
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//
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// From ixmca.c
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//
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UCHAR MsgMCEPending[] = MSG_MCE_PENDING;
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WCHAR rgzSessionManager[] = L"Session Manager";
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WCHAR rgzEnableMCE[] = L"EnableMCE";
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WCHAR rgzEnableMCA[] = L"EnableMCA";
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//
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// Timers
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//
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ULONG HalpProc0TSCHz;
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#ifdef ALLOC_DATA_PRAGMA
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#pragma data_seg()
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#endif
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ULONG HalpFeatureBits = 0;
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UCHAR HalpDevPolarity [4][2] = {
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//
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// Edge Level
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{ CFG_HIGH, CFG_LOW }, // 00 - bus def
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{ CFG_HIGH, CFG_HIGH }, // 01 - high
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{ CFG_HIGH, CFG_LOW }, // 10 - undefined
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{ CFG_LOW, CFG_LOW } // 11 - low
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};
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UCHAR HalpDevLevel [2][4] = {
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// must-be must-be
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// edge level edge level
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{ CFG_EDGE, CFG_EDGE, CFG_EDGE, CFG_ERR_LEVEL }, // 0 - edge
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{ CFG_LEVEL, CFG_LEVEL, CFG_ERR_EDGE, CFG_LEVEL } // 1 - level
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};
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//
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// Stuff for sleep or hibernate.
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//
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MOTHERBOARD_CONTEXT HalpMotherboardState = {0};
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BOOLEAN HalpOwnedDisplayBeforeSleep = FALSE;
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volatile BOOLEAN HalpHiberInProgress = FALSE;
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BOOLEAN HalpDisableHibernate = FALSE;
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USHORT HalpPciIrqMask = 0;
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USHORT HalpEisaIrqMask = 0;
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USHORT HalpEisaIrqIgnore = 0x1000;
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//
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// from mpdetect.c (needed because we reparse MPS table on hibernate resume)
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//
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UCHAR rgzNoMpsTable[] = "HAL: No MPS Table Found\n";
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UCHAR rgzNoApic[] = "HAL: No IO APIC Found\n";
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UCHAR rgzBadApicVersion[] = "HAL: Bad APIC Version\n";
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UCHAR rgzApicNotVerified[] = "HAL: APIC not verified\n";
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UCHAR rgzMPPTRCheck[] = "HAL: MP_PTR invalid checksum\n";
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UCHAR rgzNoMPTable[] = "HAL: MPS MP structure not found\n";
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UCHAR rgzMPSBadSig[] = "HAL: MPS table invalid signature\n";
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UCHAR rgzMPSBadCheck[] = "HAL: MPS table invalid checksum\n";
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UCHAR rgzBadDefault[] = "HAL: MPS default configuration unknown\n";
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UCHAR rgzNoMem[] = "HAL: Out of Memory\n";
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//
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// PAGELK handle
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//
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PVOID HalpSleepPageLock = NULL;
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PVOID HalpSleepPage16Lock = NULL;
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//
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// Timer watchdog variables
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//
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ULONG HalpTimerWatchdogEnabled = 0;
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ULONG HalpTimerWatchdogStorageOverflow = 0;
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PVOID HalpTimerWatchdogCurFrame;
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PVOID HalpTimerWatchdogLastFrame;
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PCHAR HalpTimerWatchdogStorage;
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#ifndef ACPI_HAL
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PCMPBUSTRANS HalpTypeTranslation[] = {
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// "INTERN", can't be interface_type internal
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"CBUS ", FALSE, CFG_EDGE, CBus, NULL, 0, 0,
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"CBUSII", FALSE, CFG_EDGE, CBus, NULL, 0, 0,
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"EISA ", FALSE, CFG_EDGE, Eisa, HalpAddEisaBus, EisaConfiguration, 0,
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"ISA ", FALSE, CFG_EDGE, Eisa, HalpAddEisaBus, EisaConfiguration, 0,
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"MCA ", FALSE, CFG_MB_LEVEL, MicroChannel, NULL, 0, 0,
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"MPI ", FALSE, CFG_EDGE, MPIBus, NULL, 0, 0,
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"MPSA ", FALSE, CFG_EDGE, MPSABus, NULL, 0, 0,
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"NUBUS ", FALSE, CFG_EDGE, NuBus, NULL, 0, 0,
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"PCI ", TRUE, CFG_MB_LEVEL, PCIBus, HalpAddPciBus, PCIConfiguration, sizeof (PCIPBUSDATA),
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"PCMCIA", FALSE, CFG_EDGE, PCMCIABus, NULL, 0, 0,
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"TC ", FALSE, CFG_EDGE, TurboChannel, NULL, 0, 0,
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"VL ", FALSE, CFG_EDGE, Eisa, HalpAddEisaBus, EisaConfiguration, 0,
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"VME ", FALSE, CFG_EDGE, VMEBus, NULL, 0, 0,
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"NEC98 ", FALSE, CFG_EDGE, Isa, HalpAddEisaBus, EisaConfiguration, 0,
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NULL, FALSE, CFG_EDGE, MaximumInterfaceType, NULL, 0, 0
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} ;
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#endif
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UCHAR HalpInitLevel [4][4] = {
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// must-be must-be
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// edge level edge level
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{ CFG_EDGE, CFG_LEVEL, CFG_MB_EDGE, CFG_MB_LEVEL }, // 00 - bus def
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{ CFG_MB_EDGE, CFG_MB_EDGE, CFG_MB_EDGE, CFG_ERR_MB_LEVEL }, // 01 - edge
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{ CFG_ERR_EDGE, CFG_ERR_LEVEL, CFG_ERR_MB_EDGE, CFG_ERR_MB_LEVEL }, // 10 - undefined
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{ CFG_MB_LEVEL, CFG_MB_LEVEL, CFG_ERR_MB_EDGE, CFG_MB_LEVEL } // 11 - level
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};
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BOOLEAN HalpELCRChecked;
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//
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// From mpaddr.c
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//
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USHORT HalpIoCompatibleRangeList0[] = {
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0x0100, 0x03ff, 0x0500, 0x07FF, 0x0900, 0x0BFF, 0x0D00, 0x0FFF,
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0, 0
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};
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USHORT HalpIoCompatibleRangeList1[] = {
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0x03B0, 0x03BB, 0x03C0, 0x03DF, 0x07B0, 0x07BB, 0x07C0, 0x07DF,
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0x0BB0, 0x0BBB, 0x0BC0, 0x0BDF, 0x0FB0, 0x0FBB, 0x0FC0, 0x0FDF,
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0, 0
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};
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