202 lines
5.3 KiB
C
202 lines
5.3 KiB
C
//----------------------------------------------------------------------------
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//
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// AMD64 register definitions.
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//
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// Copyright (C) Microsoft Corporation, 2000.
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//
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//----------------------------------------------------------------------------
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#ifndef __AMD64_REG_H__
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#define __AMD64_REG_H__
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//
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// x86 common registers.
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//
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#define AMD64_RAX X86_NAX
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#define AMD64_RCX X86_NCX
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#define AMD64_RDX X86_NDX
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#define AMD64_RBX X86_NBX
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#define AMD64_RSP X86_NSP
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#define AMD64_RBP X86_NBP
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#define AMD64_RSI X86_NSI
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#define AMD64_RDI X86_NDI
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#define AMD64_RIP X86_NIP
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#define AMD64_EFL X86_NFL
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#define AMD64_CS X86_NCS
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#define AMD64_DS X86_NDS
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#define AMD64_ES X86_NES
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#define AMD64_FS X86_NFS
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#define AMD64_GS X86_NGS
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#define AMD64_SS X86_NSS
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#define AMD64_SEG_FIRST X86_NSEG_FIRST
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#define AMD64_SEG_LAST X86_NSEG_LAST
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//
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// AMD64 registers.
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//
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#define AMD64_R8 17
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#define AMD64_R9 18
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#define AMD64_R10 19
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#define AMD64_R11 20
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#define AMD64_R12 21
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#define AMD64_R13 22
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#define AMD64_R14 23
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#define AMD64_R15 24
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#define AMD64_CR0 25
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#define AMD64_CR2 26
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#define AMD64_CR3 27
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#define AMD64_CR4 28
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#define AMD64_CR8 29
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#define AMD64_DR0 30
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#define AMD64_DR1 31
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#define AMD64_DR2 32
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#define AMD64_DR3 33
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#define AMD64_DR6 34
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#define AMD64_DR7 35
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#define AMD64_GDTR 36
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#define AMD64_GDTL 37
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#define AMD64_IDTR 38
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#define AMD64_IDTL 39
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#define AMD64_TR 40
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#define AMD64_LDTR 41
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// Floating-point registers:
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#define AMD64_FPCW 50
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#define AMD64_FPSW 51
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#define AMD64_FPTW 52
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#define AMD64_FPCTRL_FIRST AMD64_FPCW
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#define AMD64_FPCTRL_LAST AMD64_FPTW
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#define AMD64_ST0 53
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#define AMD64_ST1 54
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#define AMD64_ST2 55
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#define AMD64_ST3 56
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#define AMD64_ST4 57
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#define AMD64_ST5 58
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#define AMD64_ST6 59
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#define AMD64_ST7 60
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#define AMD64_ST_FIRST AMD64_ST0
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#define AMD64_ST_LAST AMD64_ST7
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// MMX registers:
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#define AMD64_MM0 61
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#define AMD64_MM1 62
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#define AMD64_MM2 63
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#define AMD64_MM3 64
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#define AMD64_MM4 65
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#define AMD64_MM5 66
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#define AMD64_MM6 67
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#define AMD64_MM7 68
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#define AMD64_MM_FIRST AMD64_MM0
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#define AMD64_MM_LAST AMD64_MM7
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// SSE registers:
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#define AMD64_MXCSR 69
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#define AMD64_XMM0 70
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#define AMD64_XMM1 71
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#define AMD64_XMM2 72
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#define AMD64_XMM3 73
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#define AMD64_XMM4 74
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#define AMD64_XMM5 75
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#define AMD64_XMM6 76
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#define AMD64_XMM7 77
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#define AMD64_XMM8 78
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#define AMD64_XMM9 79
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#define AMD64_XMM10 80
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#define AMD64_XMM11 81
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#define AMD64_XMM12 82
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#define AMD64_XMM13 83
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#define AMD64_XMM14 84
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#define AMD64_XMM15 85
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#define AMD64_XMM_FIRST AMD64_XMM0
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#define AMD64_XMM_LAST AMD64_XMM15
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#define AMD64_EAX 100
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#define AMD64_ECX 101
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#define AMD64_EDX 102
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#define AMD64_EBX 103
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#define AMD64_ESP 104
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#define AMD64_EBP 105
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#define AMD64_ESI 106
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#define AMD64_EDI 107
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#define AMD64_R8D 108
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#define AMD64_R9D 109
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#define AMD64_R10D 110
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#define AMD64_R11D 111
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#define AMD64_R12D 112
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#define AMD64_R13D 113
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#define AMD64_R14D 114
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#define AMD64_R15D 115
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#define AMD64_EIP 116
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#define AMD64_AX 117
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#define AMD64_CX 118
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#define AMD64_DX 119
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#define AMD64_BX 120
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#define AMD64_SP 121
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#define AMD64_BP 122
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#define AMD64_SI 123
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#define AMD64_DI 124
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#define AMD64_R8W 125
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#define AMD64_R9W 126
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#define AMD64_R10W 127
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#define AMD64_R11W 128
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#define AMD64_R12W 129
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#define AMD64_R13W 130
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#define AMD64_R14W 131
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#define AMD64_R15W 132
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#define AMD64_IP 133
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#define AMD64_FL 134
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#define AMD64_AL 135
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#define AMD64_CL 136
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#define AMD64_DL 137
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#define AMD64_BL 138
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#define AMD64_SPL 139
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#define AMD64_BPL 140
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#define AMD64_SIL 141
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#define AMD64_DIL 142
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#define AMD64_R8B 143
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#define AMD64_R9B 144
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#define AMD64_R10B 145
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#define AMD64_R11B 146
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#define AMD64_R12B 147
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#define AMD64_R13B 148
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#define AMD64_R14B 149
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#define AMD64_R15B 150
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#define AMD64_AH 151
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#define AMD64_CH 152
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#define AMD64_DH 153
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#define AMD64_BH 154
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#define AMD64_IOPL 200
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#define AMD64_OF 201
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#define AMD64_DF 202
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#define AMD64_IF 203
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#define AMD64_TF 204
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#define AMD64_SF 205
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#define AMD64_ZF 206
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#define AMD64_AF 207
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#define AMD64_PF 208
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#define AMD64_CF 209
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#define AMD64_VIP 210
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#define AMD64_VIF 211
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#define AMD64_SUBREG_BASE AMD64_EAX
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#endif // #ifndef __AMD64_AMD64_H__
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