forked from AbleOS/ableos
551 lines
16 KiB
Rust
551 lines
16 KiB
Rust
/*
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* Copyright (c) 2022, Umut İnan Erdoğan <umutinanerdogan@pm.me>
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*
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* SPDX-License-Identifier: MPL-2.0
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*/
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use core::mem;
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use core::num::TryFromIntError;
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use x86_64::instructions::port::Port;
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use x86_64::instructions::{hlt, interrupts};
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use x86_64::structures::paging::{FrameAllocator, FrameDeallocator};
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// FIXME: platform agnostic paging stuff
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use x86_64::structures::paging::{mapper::MapToError, Mapper, Page, PhysFrame, Size4KiB};
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use x86_64::VirtAddr;
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use crate::arch::memory::BootInfoFrameAllocator;
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use crate::devices::pci::check_device;
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use super::PciDeviceInfo;
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// FIXME: un-hardcode these
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const PRDT_START: u64 = 0xffff_ffff_0000_0000;
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const BUFFER_START: u64 = 0xffff_ffff_0000_1000;
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/// Bus Master IDE Command
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const BMIC_OFFSET: u16 = 0;
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/// Bus Master IDE Status
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const BMIS_OFFSET: u16 = 2;
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/// Bus Master IDE Descriptor Table Pointer
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const BMIDTP_OFFSET: u16 = 4;
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/// Bus Master IDE Secondary Offset
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const BMI_SECONDARY: u16 = 8;
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/// Primary command block offset
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const PRIMARY_COMMAND: u16 = 0x01F0;
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/// Secondary command block offset
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const SECONDARY_COMMAND: u16 = 0x0170;
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/// Data register offset
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const DATA_OFFSET: u16 = 0;
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/// Sector count register offset
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const SECCOUNT_OFFSET: u16 = 2;
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/// LBA0 register offset
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const LBA0_OFFSET: u16 = 3;
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/// LBA1 register offset
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const LBA1_OFFSET: u16 = 4;
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/// LBA2 register offset
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const LBA2_OFFSET: u16 = 5;
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/// Drive/Head register offset
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const DRIVE_HEAD_OFFSET: u16 = 6;
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/// Command/status register offset
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const COMMAND_STATUS_OFFSET: u16 = 7;
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/// Secondary control block offset
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const SECONDARY_CONTROL: u16 = 0x0374;
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/// Primary control block offset
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const PRIMARY_CONTROL: u16 = 0x03F4;
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/// Alternative status offset
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const ALT_STATUS_OFFSET: u16 = 2;
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/// ATA identification command
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const CMD_IDENTIFY: u8 = 0xEC;
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/// ATA read using LBA48 DMA command
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const CMD_READ_DMA_EXT: u8 = 0x25;
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pub struct PiixIde {
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device_info: PciDeviceInfo,
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ide_devices: Vec<IdeDevice>,
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prdt_frame: Option<PhysFrame>,
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buffer_frames: Option<Vec<PhysFrame>>,
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bmiba: u16,
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}
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impl PiixIde {
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// FIXME: make this return a Result
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pub fn new(bus: u8, device: u8) -> Option<Self> {
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let device_info = check_device(bus, device)?;
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device_info.enable_bus_mastering();
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let idetim = unsafe { device_info.read(0, 0x40) };
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trace!("idetim: {idetim:b}");
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// FIXME: enable the right bits in idetim (and sidetim) to use fast timings
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let mut ide_devices = Vec::with_capacity(4);
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for ch in 0..2 {
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let channel = if ch == 0 {
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Channel::Primary
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} else {
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Channel::Secondary
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};
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'drive: for dr in 0..2 {
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let drive = if dr == 0 { Drive::Master } else { Drive::Slave };
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unsafe {
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select_drive(drive, channel);
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// FIXME: clear sector count and lba0, lba1, lba2 registers
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let status = ata_send_command(CMD_IDENTIFY, channel);
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if status == 0 {
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continue; // If status = 0, no device
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}
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loop {
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let status = {
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let addr = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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} + COMMAND_STATUS_OFFSET;
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Port::<u8>::new(addr).read()
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};
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if status & 1 == 1 {
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// if error (bit 0), device is not ATA
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// FIXME: ATAPI devices
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continue 'drive;
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}
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if !((status >> 7) & 1 == 1) && (status >> 3) & 1 == 1 {
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// BSY cleared, DRQ set, everything is right
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break;
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}
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}
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// Read identification space of device
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let addr = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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} + DATA_OFFSET;
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let mut buffer = [0_u8; 512];
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read_dword_buffer(addr, buffer.as_mut_ptr() as *mut _, 128);
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// for (i, byte) in buffer.iter().enumerate() {
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// if byte.is_ascii() {
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// trace!("byte {i}: {byte:b}, ascii: {}", *byte as char);
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// } else {
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// trace!("byte {i}: {byte:b}");
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// }
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// }
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if buffer[99] & 1 != 1 {
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// FIXME: PIO mode support
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error!("IDE drive {channel:?}/{drive:?} does not support DMA");
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continue;
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}
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if (buffer[167] >> 2) & 1 != 1 {
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// FIXME: 24-bit LBA and CHS support
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error!("IDE drive {channel:?}/{drive:?} does not support 48-bit LBA");
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}
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let size = buffer[200] as u64
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| (buffer[201] as u64) << 8
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| (buffer[202] as u64) << 16
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| (buffer[203] as u64) << 24
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| (buffer[204] as u64) << 32
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| (buffer[205] as u64) << 40
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| (buffer[206] as u64) << 48
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| (buffer[207] as u64) << 54;
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trace!("IDE drive {channel:?}/{drive:?} has {size} sectors");
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ide_devices.push(IdeDevice {
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channel,
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drive,
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size,
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});
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}
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}
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}
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let bmiba = device_info.bar(4) & 0xFFFFFFFC;
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Some(Self {
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device_info,
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ide_devices,
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prdt_frame: None,
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buffer_frames: None,
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bmiba: bmiba.try_into().ok()?,
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})
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}
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pub fn allocate_dma_frame(
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&mut self,
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mapper: &mut impl Mapper<Size4KiB>,
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frame_allocator: &mut BootInfoFrameAllocator,
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) -> Result<(), MapToError<Size4KiB>> {
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use x86_64::structures::paging::PageTableFlags as Flags;
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let prdt_frame = frame_allocator
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.allocate_frame()
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.ok_or(MapToError::FrameAllocationFailed)?;
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let buffer_frames = {
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let mut frame = frame_allocator
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.allocate_frame()
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.ok_or(MapToError::FrameAllocationFailed)?;
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while !frame.start_address().is_aligned(0x10000u64) {
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unsafe {
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frame_allocator.deallocate_frame(frame);
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}
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frame = frame_allocator
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.allocate_frame()
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.ok_or(MapToError::FrameAllocationFailed)?;
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}
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let mut frames = Vec::with_capacity(16);
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frames.push(frame);
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for _ in 0..15 {
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let frame = frame_allocator
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.allocate_frame()
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.ok_or(MapToError::FrameAllocationFailed)?;
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frames.push(frame);
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}
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frames
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};
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let flags = Flags::NO_CACHE | Flags::PRESENT | Flags::WRITABLE;
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unsafe {
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mapper
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.map_to(
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Page::containing_address(VirtAddr::new(PRDT_START)),
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prdt_frame,
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flags,
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frame_allocator,
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)?
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.flush();
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for (i, frame) in buffer_frames.iter().enumerate() {
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mapper
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.map_to(
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Page::containing_address(VirtAddr::new(BUFFER_START + i as u64 * 0x1000)),
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*frame,
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flags,
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frame_allocator,
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)?
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.flush()
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}
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}
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self.prdt_frame = Some(prdt_frame);
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self.buffer_frames = Some(buffer_frames);
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Ok(())
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}
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pub fn read(&mut self) -> Result<(), TryFromIntError> {
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// prepare PRD table
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let prd = PRDT_START as *mut PhysRegionDescriptor;
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unsafe {
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(*prd).data_buffer = self.buffer_frames.as_ref().unwrap()[0]
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.start_address()
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.as_u64()
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.try_into()?;
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// we want to read 512 bytes
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(*prd).byte_count = 512;
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// this is the end of table
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(*prd).eot = 1 << 7;
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// this byte is reserved, we should probably set it to 0
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(*prd)._0 = 0;
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}
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unsafe {
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self.load_prdt(Channel::Primary);
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self.stop(Channel::Primary);
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self.set_read(Channel::Primary);
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self.clear_bmi_status(Channel::Primary);
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select_drive(Drive::Master, Channel::Primary);
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set_lba(Channel::Primary, 0, 1);
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ata_send_command(CMD_READ_DMA_EXT, Channel::Primary);
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self.start(Channel::Primary);
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loop {
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let status = self.bmi_status(Channel::Primary);
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trace!("read status: 0b{status:b}");
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// Bit 2 (INT) set?
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if (status >> 2) & 1 == 1 {
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break;
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}
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}
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// FIXME: error handling
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// Stop DMA
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self.stop(Channel::Primary);
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// Clear the interrupt bit
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self.clear_bmi_status(Channel::Primary);
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for i in 0..512 {
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let addr = (BUFFER_START + i) as *mut u8;
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trace!("byte {i}: {}", *addr);
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}
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}
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Ok(())
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}
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pub fn device_info(&self) -> PciDeviceInfo {
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self.device_info
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}
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unsafe fn load_prdt(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIDTP_OFFSET;
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Port::<u32>::new(addr).write(
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self.prdt_frame
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.unwrap()
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.start_address()
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.as_u64()
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.try_into()
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.unwrap(),
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);
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}
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unsafe fn start(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIC_OFFSET;
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let mut port: Port<u8> = Port::new(addr);
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let mut bmic = port.read();
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// start transfer
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bmic |= 1;
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// write the new bmic
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port.write(bmic);
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}
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unsafe fn stop(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIC_OFFSET;
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let mut port: Port<u8> = Port::new(addr);
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let mut bmic = port.read();
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// stop ongoing transfer
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bmic &= !1;
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// write the new bmic
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port.write(bmic);
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}
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unsafe fn set_read(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIC_OFFSET;
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let mut port: Port<u8> = Port::new(addr);
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let mut bmic = port.read();
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// mark bit 3 as 0 (read)
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bmic &= !(1 << 3);
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// write the new bmic
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port.write(bmic);
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}
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unsafe fn set_write(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIC_OFFSET;
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let mut port: Port<u8> = Port::new(addr);
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let mut bmic = port.read();
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// mark bit 3 as 1 (write)
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bmic |= 1 << 3;
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// write the new bmic
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port.write(bmic);
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}
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unsafe fn bmi_status(&self, channel: Channel) -> u8 {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIS_OFFSET;
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let mut port = Port::new(addr);
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port.read()
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}
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unsafe fn clear_bmi_status(&self, channel: Channel) {
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let addr = if channel.secondary() {
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BMI_SECONDARY
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} else {
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0
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} + self.bmiba
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+ BMIS_OFFSET;
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let mut port: Port<u8> = Port::new(addr);
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let mut bmis = port.read();
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// write 1 to bits 1 (DMA error) and 2 (int status) which clears them
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bmis |= 1 << 1 | 1 << 2;
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// write the new bmis
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port.write(bmis);
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}
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}
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unsafe fn select_drive(drive: Drive, channel: Channel) {
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let addr = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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} + DRIVE_HEAD_OFFSET;
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let mut port: Port<u8> = Port::new(addr);
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// FIXME: CHS support
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let drive_command = if drive.slave() {
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// slave & LBA
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0b11110000
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} else {
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// master & LBA
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0b11100000
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};
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// write the new drive/head register
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port.write(drive_command);
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ata_delay(channel);
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}
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/// Send ATA command and read status afterwards
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unsafe fn ata_send_command(command: u8, channel: Channel) -> u8 {
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let addr = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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} + COMMAND_STATUS_OFFSET;
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let mut port = Port::new(addr);
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port.write(command);
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ata_delay(channel);
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port.read()
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}
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/// Read the alternate status register 14 times to create a ~420ns delay
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unsafe fn ata_delay(channel: Channel) {
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let addr = if channel.secondary() {
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SECONDARY_CONTROL
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} else {
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PRIMARY_CONTROL
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} + ALT_STATUS_OFFSET;
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let mut port: Port<u8> = Port::new(addr);
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for _ in 0..14 {
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port.read();
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}
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}
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/// Set LBA and sector count registers. sector_count of 0 means 65536 sectors
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unsafe fn set_lba(channel: Channel, lba: u64, sector_count: u16) {
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// FIXME: CHS and LBA24 support
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assert!(lba < 0xFFFFFFFFFFFF);
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let command_block = if channel.secondary() {
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SECONDARY_COMMAND
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} else {
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PRIMARY_COMMAND
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};
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let mut seccount = Port::new(command_block + SECCOUNT_OFFSET);
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let mut lba0 = Port::new(command_block + LBA0_OFFSET);
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let mut lba1 = Port::new(command_block + LBA1_OFFSET);
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let mut lba2 = Port::new(command_block + LBA2_OFFSET);
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let lba_bytes = lba.to_le_bytes();
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let sector_count_bytes = sector_count.to_le_bytes();
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// write the new LBA & sector count registers
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// if LBA48 {
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seccount.write(sector_count_bytes[1]);
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lba0.write(lba_bytes[3]);
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lba1.write(lba_bytes[4]);
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lba2.write(lba_bytes[5]);
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// }
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seccount.write(sector_count_bytes[0]);
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lba0.write(lba_bytes[0]);
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lba1.write(lba_bytes[1]);
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lba2.write(lba_bytes[2]);
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}
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unsafe fn read_dword_buffer(port: u16, buffer: *mut u32, mut count: u32) {
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// FIXME: this assumes x86-64
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interrupts::without_interrupts(|| {
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asm!("
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cld
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repne
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insd",
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in("di") buffer,
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in("dx") port,
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inout("cx") count,
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)
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});
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}
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struct IdeDevice {
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pub channel: Channel,
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pub drive: Drive,
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pub size: u64, // in sectors
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// FIXME: model
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}
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#[derive(Copy, Clone, Debug)]
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enum Channel {
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Primary,
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Secondary,
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}
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impl Channel {
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fn secondary(&self) -> bool {
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matches!(self, Self::Secondary)
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}
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}
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#[derive(Copy, Clone, Debug)]
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enum Drive {
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Master,
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Slave,
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}
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impl Drive {
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fn slave(&self) -> bool {
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matches!(self, Self::Slave)
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}
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}
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#[repr(C, packed)]
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struct PhysRegionDescriptor {
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/// Pointer to the data buffer
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pub data_buffer: u32,
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/// Byte count, 64K maximum per PRD transfer. 0 means 64K
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pub byte_count: u16,
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/// Reserved byte
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pub _0: u8,
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/// MSB marks end of transfer
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pub eot: u8,
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}
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