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Signed-off-by: AsyaTheAbove <asya@waifu.club>
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AsyaTheAbove 2023-08-19 18:03:46 +03:00
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/target

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# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 3
[[package]]
name = "bitflags"
version = "2.4.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b4682ae6287fcf752ecaabbfcc7b6f9b72aa33933dc23a554d853aea8eea8635"
[[package]]
name = "copycat"
version = "0.1.0"
dependencies = [
"bitflags",
]

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[package]
name = "copycat"
version = "0.1.0"
edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
bitflags = "2.4.0"

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Mozilla Public License Version 2.0
==================================
1. Definitions
--------------
1.1. "Contributor"
means each individual or legal entity that creates, contributes to
the creation of, or owns Covered Software.
1.2. "Contributor Version"
means the combination of the Contributions of others (if any) used
by a Contributor and that particular Contributor's Contribution.
1.3. "Contribution"
means Covered Software of a particular Contributor.
1.4. "Covered Software"
means Source Code Form to which the initial Contributor has attached
the notice in Exhibit A, the Executable Form of such Source Code
Form, and Modifications of such Source Code Form, in each case
including portions thereof.
1.5. "Incompatible With Secondary Licenses"
means
(a) that the initial Contributor has attached the notice described
in Exhibit B to the Covered Software; or
(b) that the Covered Software was made available under the terms of
version 1.1 or earlier of the License, but not also under the
terms of a Secondary License.
1.6. "Executable Form"
means any form of the work other than Source Code Form.
1.7. "Larger Work"
means a work that combines Covered Software with other material, in
a separate file or files, that is not Covered Software.
1.8. "License"
means this document.
1.9. "Licensable"
means having the right to grant, to the maximum extent possible,
whether at the time of the initial grant or subsequently, any and
all of the rights conveyed by this License.
1.10. "Modifications"
means any of the following:
(a) any file in Source Code Form that results from an addition to,
deletion from, or modification of the contents of Covered
Software; or
(b) any new file in Source Code Form that contains any Covered
Software.
1.11. "Patent Claims" of a Contributor
means any patent claim(s), including without limitation, method,
process, and apparatus claims, in any patent Licensable by such
Contributor that would be infringed, but for the grant of the
License, by the making, using, selling, offering for sale, having
made, import, or transfer of either its Contributions or its
Contributor Version.
1.12. "Secondary License"
means either the GNU General Public License, Version 2.0, the GNU
Lesser General Public License, Version 2.1, the GNU Affero General
Public License, Version 3.0, or any later versions of those
licenses.
1.13. "Source Code Form"
means the form of the work preferred for making modifications.
1.14. "You" (or "Your")
means an individual or a legal entity exercising rights under this
License. For legal entities, "You" includes any entity that
controls, is controlled by, or is under common control with You. For
purposes of this definition, "control" means (a) the power, direct
or indirect, to cause the direction or management of such entity,
whether by contract or otherwise, or (b) ownership of more than
fifty percent (50%) of the outstanding shares or beneficial
ownership of such entity.
2. License Grants and Conditions
--------------------------------
2.1. Grants
Each Contributor hereby grants You a world-wide, royalty-free,
non-exclusive license:
(a) under intellectual property rights (other than patent or trademark)
Licensable by such Contributor to use, reproduce, make available,
modify, display, perform, distribute, and otherwise exploit its
Contributions, either on an unmodified basis, with Modifications, or
as part of a Larger Work; and
(b) under Patent Claims of such Contributor to make, use, sell, offer
for sale, have made, import, and otherwise transfer either its
Contributions or its Contributor Version.
2.2. Effective Date
The licenses granted in Section 2.1 with respect to any Contribution
become effective for each Contribution on the date the Contributor first
distributes such Contribution.
2.3. Limitations on Grant Scope
The licenses granted in this Section 2 are the only rights granted under
this License. No additional rights or licenses will be implied from the
distribution or licensing of Covered Software under this License.
Notwithstanding Section 2.1(b) above, no patent license is granted by a
Contributor:
(a) for any code that a Contributor has removed from Covered Software;
or
(b) for infringements caused by: (i) Your and any other third party's
modifications of Covered Software, or (ii) the combination of its
Contributions with other software (except as part of its Contributor
Version); or
(c) under Patent Claims infringed by Covered Software in the absence of
its Contributions.
This License does not grant any rights in the trademarks, service marks,
or logos of any Contributor (except as may be necessary to comply with
the notice requirements in Section 3.4).
2.4. Subsequent Licenses
No Contributor makes additional grants as a result of Your choice to
distribute the Covered Software under a subsequent version of this
License (see Section 10.2) or under the terms of a Secondary License (if
permitted under the terms of Section 3.3).
2.5. Representation
Each Contributor represents that the Contributor believes its
Contributions are its original creation(s) or it has sufficient rights
to grant the rights to its Contributions conveyed by this License.
2.6. Fair Use
This License is not intended to limit any rights You have under
applicable copyright doctrines of fair use, fair dealing, or other
equivalents.
2.7. Conditions
Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted
in Section 2.1.
3. Responsibilities
-------------------
3.1. Distribution of Source Form
All distribution of Covered Software in Source Code Form, including any
Modifications that You create or to which You contribute, must be under
the terms of this License. You must inform recipients that the Source
Code Form of the Covered Software is governed by the terms of this
License, and how they can obtain a copy of this License. You may not
attempt to alter or restrict the recipients' rights in the Source Code
Form.
3.2. Distribution of Executable Form
If You distribute Covered Software in Executable Form then:
(a) such Covered Software must also be made available in Source Code
Form, as described in Section 3.1, and You must inform recipients of
the Executable Form how they can obtain a copy of such Source Code
Form by reasonable means in a timely manner, at a charge no more
than the cost of distribution to the recipient; and
(b) You may distribute such Executable Form under the terms of this
License, or sublicense it under different terms, provided that the
license for the Executable Form does not attempt to limit or alter
the recipients' rights in the Source Code Form under this License.
3.3. Distribution of a Larger Work
You may create and distribute a Larger Work under terms of Your choice,
provided that You also comply with the requirements of this License for
the Covered Software. If the Larger Work is a combination of Covered
Software with a work governed by one or more Secondary Licenses, and the
Covered Software is not Incompatible With Secondary Licenses, this
License permits You to additionally distribute such Covered Software
under the terms of such Secondary License(s), so that the recipient of
the Larger Work may, at their option, further distribute the Covered
Software under the terms of either this License or such Secondary
License(s).
3.4. Notices
You may not remove or alter the substance of any license notices
(including copyright notices, patent notices, disclaimers of warranty,
or limitations of liability) contained within the Source Code Form of
the Covered Software, except that You may alter any license notices to
the extent required to remedy known factual inaccuracies.
3.5. Application of Additional Terms
You may choose to offer, and to charge a fee for, warranty, support,
indemnity or liability obligations to one or more recipients of Covered
Software. However, You may do so only on Your own behalf, and not on
behalf of any Contributor. You must make it absolutely clear that any
such warranty, support, indemnity, or liability obligation is offered by
You alone, and You hereby agree to indemnify every Contributor for any
liability incurred by such Contributor as a result of warranty, support,
indemnity or liability terms You offer. You may include additional
disclaimers of warranty and limitations of liability specific to any
jurisdiction.
4. Inability to Comply Due to Statute or Regulation
---------------------------------------------------
If it is impossible for You to comply with any of the terms of this
License with respect to some or all of the Covered Software due to
statute, judicial order, or regulation then You must: (a) comply with
the terms of this License to the maximum extent possible; and (b)
describe the limitations and the code they affect. Such description must
be placed in a text file included with all distributions of the Covered
Software under this License. Except to the extent prohibited by statute
or regulation, such description must be sufficiently detailed for a
recipient of ordinary skill to be able to understand it.
5. Termination
--------------
5.1. The rights granted under this License will terminate automatically
if You fail to comply with any of its terms. However, if You become
compliant, then the rights granted under this License from a particular
Contributor are reinstated (a) provisionally, unless and until such
Contributor explicitly and finally terminates Your grants, and (b) on an
ongoing basis, if such Contributor fails to notify You of the
non-compliance by some reasonable means prior to 60 days after You have
come back into compliance. Moreover, Your grants from a particular
Contributor are reinstated on an ongoing basis if such Contributor
notifies You of the non-compliance by some reasonable means, this is the
first time You have received notice of non-compliance with this License
from such Contributor, and You become compliant prior to 30 days after
Your receipt of the notice.
5.2. If You initiate litigation against any entity by asserting a patent
infringement claim (excluding declaratory judgment actions,
counter-claims, and cross-claims) alleging that a Contributor Version
directly or indirectly infringes any patent, then the rights granted to
You by any and all Contributors for the Covered Software under Section
2.1 of this License shall terminate.
5.3. In the event of termination under Sections 5.1 or 5.2 above, all
end user license agreements (excluding distributors and resellers) which
have been validly granted by You or Your distributors under this License
prior to termination shall survive termination.
************************************************************************
* *
* 6. Disclaimer of Warranty *
* ------------------------- *
* *
* Covered Software is provided under this License on an "as is" *
* basis, without warranty of any kind, either expressed, implied, or *
* statutory, including, without limitation, warranties that the *
* Covered Software is free of defects, merchantable, fit for a *
* particular purpose or non-infringing. The entire risk as to the *
* quality and performance of the Covered Software is with You. *
* Should any Covered Software prove defective in any respect, You *
* (not any Contributor) assume the cost of any necessary servicing, *
* repair, or correction. This disclaimer of warranty constitutes an *
* essential part of this License. No use of any Covered Software is *
* authorized under this License except under this disclaimer. *
* *
************************************************************************
************************************************************************
* *
* 7. Limitation of Liability *
* -------------------------- *
* *
* Under no circumstances and under no legal theory, whether tort *
* (including negligence), contract, or otherwise, shall any *
* Contributor, or anyone who distributes Covered Software as *
* permitted above, be liable to You for any direct, indirect, *
* special, incidental, or consequential damages of any character *
* including, without limitation, damages for lost profits, loss of *
* goodwill, work stoppage, computer failure or malfunction, or any *
* and all other commercial damages or losses, even if such party *
* shall have been informed of the possibility of such damages. This *
* limitation of liability shall not apply to liability for death or *
* personal injury resulting from such party's negligence to the *
* extent applicable law prohibits such limitation. Some *
* jurisdictions do not allow the exclusion or limitation of *
* incidental or consequential damages, so this exclusion and *
* limitation may not apply to You. *
* *
************************************************************************
8. Litigation
-------------
Any litigation relating to this License may be brought only in the
courts of a jurisdiction where the defendant maintains its principal
place of business and such litigation shall be governed by laws of that
jurisdiction, without reference to its conflict-of-law provisions.
Nothing in this Section shall prevent a party's ability to bring
cross-claims or counter-claims.
9. Miscellaneous
----------------
This License represents the complete agreement concerning the subject
matter hereof. If any provision of this License is held to be
unenforceable, such provision shall be reformed only to the extent
necessary to make it enforceable. Any law or regulation which provides
that the language of a contract shall be construed against the drafter
shall not be used to construe this License against a Contributor.
10. Versions of the License
---------------------------
10.1. New Versions
Mozilla Foundation is the license steward. Except as provided in Section
10.3, no one other than the license steward has the right to modify or
publish new versions of this License. Each version will be given a
distinguishing version number.
10.2. Effect of New Versions
You may distribute the Covered Software under the terms of the version
of the License under which You originally received the Covered Software,
or under the terms of any subsequent version published by the license
steward.
10.3. Modified Versions
If you create software not governed by this License, and you want to
create a new license for such software, you may create and use a
modified version of this License if you rename the license and remove
any references to the name of the license steward (except to note that
such modified license differs from this License).
10.4. Distributing Source Code Form that is Incompatible With Secondary
Licenses
If You choose to distribute Source Code Form that is Incompatible With
Secondary Licenses under the terms of this version of the License, the
notice described in Exhibit B of this License must be attached.
Exhibit A - Source Code Form License Notice
-------------------------------------------
This Source Code Form is subject to the terms of the Mozilla Public
License, v. 2.0. If a copy of the MPL was not distributed with this
file, You can obtain one at http://mozilla.org/MPL/2.0/.
If it is not possible or desirable to put the notice in a particular
file, then You may include the notice in a location (such as a LICENSE
file in a relevant directory) where a recipient would be likely to look
for such a notice.
You may add additional accurate notices of copyright ownership.
Exhibit B - "Incompatible With Secondary Licenses" Notice
---------------------------------------------------------
This Source Code Form is "Incompatible With Secondary Licenses", as
defined by the Mozilla Public License, v. 2.0.

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/*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
#![feature(bigint_helper_methods)]
pub mod machine;
pub mod memory;
pub mod processor;

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/*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
use crate::processor::Processor;
use crate::memory::Memory;
pub struct Machine {
cpu: Processor,
memory: Memory,
}

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/*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
use copycat::memory::{Memory, MiB};
use processor::{Instruction, Processor};
fn main() {
let mut mem = Memory::new(1 * MiB);
mem.write(0xffff0, [0x90, 0x04, 0x69, 0xF4]);
let mut cpu = Processor::default();
cpu.registers.dump();
while !cpu.halted {
let instr = Instruction::decode(&mem, &mut cpu.registers);
println!("{instr:?}");
cpu.exec(&mut mem, &instr);
cpu.registers.dump();
}
}

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/*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
use std::alloc::{alloc, dealloc, Layout};
mod consts {
#![allow(non_upper_case_globals)]
pub const KiB: u64 = 1024;
pub const MiB: u64 = 1024 * KiB;
}
pub use consts::*;
pub struct Memory {
memory: *mut u8,
memory_size: u64,
}
impl Memory {
pub fn new(size: u64) -> Self {
Self {
memory: unsafe {
alloc(Layout::from_size_align(size.try_into().unwrap(), 1 * MiB as usize).expect("layout error"))
},
memory_size: size,
}
}
pub fn read<const N: usize>(&self, address: u64) -> [u8; N] {
if address >= self.memory_size {
return [0; N];
}
unsafe {
self.memory.offset(address.try_into().unwrap()).cast::<[u8; N]>().read_unaligned()
}
}
pub fn write<const N: usize>(&mut self, address: u64, value: [u8; N]) {
if address >= self.memory_size {
return;
}
unsafe {
self.memory.offset(address.try_into().unwrap()).cast::<[u8; N]>().write_unaligned(value);
}
}
pub fn read_u8(&self, address: u64) -> u8 {
self.read::<1>(address)[0]
}
pub fn write_u8(&mut self, address: u64, value: u8) {
self.write::<1>(address, [value]);
}
pub fn read_u16(&self, address: u64) -> u16 {
u16::from_le_bytes(self.read::<2>(address))
}
pub fn write_u16(&mut self, address: u64, value: u16) {
self.write::<2>(address, value.to_le_bytes());
}
}
impl Drop for Memory {
fn drop(&mut self) {
unsafe {
dealloc(self.memory, Layout::from_size_align(self.memory_size.try_into().unwrap(), 1 * MiB as usize).expect("layout error"));
}
}
}

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/*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
use bitflags::bitflags;
use crate::memory::Memory;
use super::register::Registers;
#[derive(Clone, Debug)]
pub struct Instruction {
pub opcode: u8,
pub mnemonic: Mnemonic,
pub op1: Operand,
pub op2: Operand,
pub segment_override: SegmentOverride,
pub address: u64,
}
impl Instruction {
pub fn decode(memory: &Memory, registers: &mut Registers) -> Instruction {
let address = ((registers.cs() as u64) << 4) + registers.ip() as u64;
let mut opcode = memory.read_u8(address);
let mut size: u8 = 1;
let mut segment_override = SegmentOverride::None;
loop {
// FIXME: handle lock and rep
segment_override = match opcode {
0x26 => SegmentOverride::ES,
0x2E => SegmentOverride::CS,
0x36 => SegmentOverride::SS,
0x3E => SegmentOverride::DS,
_ => break,
};
opcode = memory.read_u8(address + size as u64);
size += 1;
}
let (mnemonic, op1ty, op2ty) = match opcode {
0x00 => (Mnemonic::Add, OperandFormat::RM8, OperandFormat::Reg8),
0x01 => (Mnemonic::Add, OperandFormat::RM16, OperandFormat::Reg16),
0x02 => (Mnemonic::Add, OperandFormat::Reg8, OperandFormat::RM8),
0x03 => (Mnemonic::Add, OperandFormat::Reg16, OperandFormat::RM16),
0x04 => (Mnemonic::Add, OperandFormat::AL, OperandFormat::Imm8),
0x05 => (Mnemonic::Add, OperandFormat::AX, OperandFormat::Imm16),
0x10 => (Mnemonic::Adc, OperandFormat::RM8, OperandFormat::Reg8),
0x11 => (Mnemonic::Adc, OperandFormat::RM16, OperandFormat::Reg16),
0x12 => (Mnemonic::Adc, OperandFormat::Reg8, OperandFormat::RM8),
0x13 => (Mnemonic::Adc, OperandFormat::Reg16, OperandFormat::RM16),
0x14 => (Mnemonic::Adc, OperandFormat::AL, OperandFormat::Imm8),
0x15 => (Mnemonic::Adc, OperandFormat::AX, OperandFormat::Imm16),
0x18 => (Mnemonic::Sbb, OperandFormat::RM8, OperandFormat::Reg8),
0x19 => (Mnemonic::Sbb, OperandFormat::RM16, OperandFormat::Reg16),
0x1A => (Mnemonic::Sbb, OperandFormat::Reg8, OperandFormat::RM8),
0x1B => (Mnemonic::Sbb, OperandFormat::Reg16, OperandFormat::RM16),
0x1C => (Mnemonic::Sbb, OperandFormat::AL, OperandFormat::Imm8),
0x1D => (Mnemonic::Sbb, OperandFormat::AX, OperandFormat::Imm16),
0x28 => (Mnemonic::Sub, OperandFormat::RM8, OperandFormat::Reg8),
0x29 => (Mnemonic::Sub, OperandFormat::RM16, OperandFormat::Reg16),
0x2A => (Mnemonic::Sub, OperandFormat::Reg8, OperandFormat::RM8),
0x2B => (Mnemonic::Sub, OperandFormat::Reg16, OperandFormat::RM16),
0x2C => (Mnemonic::Sub, OperandFormat::AL, OperandFormat::Imm8),
0x2D => (Mnemonic::Sub, OperandFormat::AX, OperandFormat::Imm16),
0x30 => (Mnemonic::Xor, OperandFormat::RM8, OperandFormat::Reg8),
0x31 => (Mnemonic::Xor, OperandFormat::RM16, OperandFormat::Reg16),
0x32 => (Mnemonic::Xor, OperandFormat::Reg8, OperandFormat::RM8),
0x33 => (Mnemonic::Xor, OperandFormat::Reg16, OperandFormat::RM16),
0x34 => (Mnemonic::Xor, OperandFormat::AL, OperandFormat::Imm8),
0x35 => (Mnemonic::Xor, OperandFormat::AX, OperandFormat::Imm16),
0x40 => (Mnemonic::Inc, OperandFormat::AX, OperandFormat::NoOperand),
0x41 => (Mnemonic::Inc, OperandFormat::CX, OperandFormat::NoOperand),
0x42 => (Mnemonic::Inc, OperandFormat::DX, OperandFormat::NoOperand),
0x43 => (Mnemonic::Inc, OperandFormat::BX, OperandFormat::NoOperand),
0x44 => (Mnemonic::Inc, OperandFormat::SP, OperandFormat::NoOperand),
0x45 => (Mnemonic::Inc, OperandFormat::BP, OperandFormat::NoOperand),
0x46 => (Mnemonic::Inc, OperandFormat::SI, OperandFormat::NoOperand),
0x47 => (Mnemonic::Inc, OperandFormat::DI, OperandFormat::NoOperand),
0x48 => (Mnemonic::Dec, OperandFormat::AX, OperandFormat::NoOperand),
0x49 => (Mnemonic::Dec, OperandFormat::CX, OperandFormat::NoOperand),
0x4A => (Mnemonic::Dec, OperandFormat::DX, OperandFormat::NoOperand),
0x4B => (Mnemonic::Dec, OperandFormat::BX, OperandFormat::NoOperand),
0x4C => (Mnemonic::Dec, OperandFormat::SP, OperandFormat::NoOperand),
0x4D => (Mnemonic::Dec, OperandFormat::BP, OperandFormat::NoOperand),
0x4E => (Mnemonic::Dec, OperandFormat::SI, OperandFormat::NoOperand),
0x4F => (Mnemonic::Dec, OperandFormat::DI, OperandFormat::NoOperand),
0x90 => (Mnemonic::Nop, OperandFormat::NoOperand, OperandFormat::NoOperand),
0xF4 => (Mnemonic::Hlt, OperandFormat::NoOperand, OperandFormat::NoOperand),
_ => (Mnemonic::Invalid, OperandFormat::NoOperand, OperandFormat::NoOperand),
};
let mut modrm = None;
if matches!(op1ty, OperandFormat::RM8 | OperandFormat::RM16 | OperandFormat::Reg8 | OperandFormat::Reg16)
|| matches!(op2ty, OperandFormat::RM8 | OperandFormat::RM16 | OperandFormat::Reg8 | OperandFormat::Reg16)
{
modrm = ModRM::from_bits(memory.read_u8(address + size as u64));
size += 1;
}
let mut match_op = |op_ty| match op_ty {
OperandFormat::NoOperand => Operand(OperandType::NoOperand, OperandSize::None),
OperandFormat::RM8 => Operand(match modrm.unwrap() & ModRM::MOD_MASK {
ModRM::MOD_DIRECT => match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::AL,
ModRM::RM_REG_1 => OperandType::CL,
ModRM::RM_REG_2 => OperandType::DL,
ModRM::RM_REG_3 => OperandType::BL,
ModRM::RM_REG_4 => OperandType::AH,
ModRM::RM_REG_5 => OperandType::CH,
ModRM::RM_REG_6 => OperandType::DH,
ModRM::RM_REG_7 => OperandType::BH,
_ => unreachable!(),
},
ModRM::MOD_0 => match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::Indirect(AddressingMode::BX_SI),
ModRM::RM_REG_1 => OperandType::Indirect(AddressingMode::BX_DI),
ModRM::RM_REG_2 => OperandType::Indirect(AddressingMode::BP_SI),
ModRM::RM_REG_3 => OperandType::Indirect(AddressingMode::BP_DI),
ModRM::RM_REG_4 => OperandType::Indirect(AddressingMode::SI),
ModRM::RM_REG_5 => OperandType::Indirect(AddressingMode::DI),
ModRM::RM_REG_6 => OperandType::Indirect(AddressingMode::Disp16({
let disp = memory.read_u16(address + size as u64);
size += 1;
disp as i16
})),
ModRM::RM_REG_7 => OperandType::Indirect(AddressingMode::BX),
_ => unreachable!()
},
ModRM::MOD_1 => {
let disp = memory.read_u8(address + size as u64) as i8;
size += 1;
match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::Indirect(AddressingMode::BX_SI_Disp8(disp)),
ModRM::RM_REG_1 => OperandType::Indirect(AddressingMode::BX_DI_Disp8(disp)),
ModRM::RM_REG_2 => OperandType::Indirect(AddressingMode::BP_SI_Disp8(disp)),
ModRM::RM_REG_3 => OperandType::Indirect(AddressingMode::BP_DI_Disp8(disp)),
ModRM::RM_REG_4 => OperandType::Indirect(AddressingMode::SI_Disp8(disp)),
ModRM::RM_REG_5 => OperandType::Indirect(AddressingMode::DI_Disp8(disp)),
ModRM::RM_REG_6 => OperandType::Indirect(AddressingMode::BP_Disp8(disp)),
ModRM::RM_REG_7 => OperandType::Indirect(AddressingMode::BX_Disp8(disp)),
_ => unreachable!(),
}
},
ModRM::MOD_2 => {
let disp = memory.read_u16(address + size as u64) as i16;
size += 2;
match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::Indirect(AddressingMode::BX_SI_Disp16(disp)),
ModRM::RM_REG_1 => OperandType::Indirect(AddressingMode::BX_DI_Disp16(disp)),
ModRM::RM_REG_2 => OperandType::Indirect(AddressingMode::BP_SI_Disp16(disp)),
ModRM::RM_REG_3 => OperandType::Indirect(AddressingMode::BP_DI_Disp16(disp)),
ModRM::RM_REG_4 => OperandType::Indirect(AddressingMode::SI_Disp16(disp)),
ModRM::RM_REG_5 => OperandType::Indirect(AddressingMode::DI_Disp16(disp)),
ModRM::RM_REG_6 => OperandType::Indirect(AddressingMode::BP_Disp16(disp)),
ModRM::RM_REG_7 => OperandType::Indirect(AddressingMode::BX_Disp16(disp)),
_ => unreachable!(),
}
},
_ => unreachable!(),
}, OperandSize::Byte),
OperandFormat::RM16 => Operand(match modrm.unwrap() & ModRM::MOD_MASK {
ModRM::MOD_DIRECT => match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::AX,
ModRM::RM_REG_1 => OperandType::CX,
ModRM::RM_REG_2 => OperandType::DX,
ModRM::RM_REG_3 => OperandType::BX,
ModRM::RM_REG_4 => OperandType::SP,
ModRM::RM_REG_5 => OperandType::BP,
ModRM::RM_REG_6 => OperandType::SI,
ModRM::RM_REG_7 => OperandType::DI,
_ => unreachable!(),
},
ModRM::MOD_0 => match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::Indirect(AddressingMode::BX_SI),
ModRM::RM_REG_1 => OperandType::Indirect(AddressingMode::BX_DI),
ModRM::RM_REG_2 => OperandType::Indirect(AddressingMode::BP_SI),
ModRM::RM_REG_3 => OperandType::Indirect(AddressingMode::BP_DI),
ModRM::RM_REG_4 => OperandType::Indirect(AddressingMode::SI),
ModRM::RM_REG_5 => OperandType::Indirect(AddressingMode::DI),
ModRM::RM_REG_6 => OperandType::Indirect(AddressingMode::Disp16({
let disp = memory.read_u16(address + size as u64);
size += 1;
disp as i16
})),
ModRM::RM_REG_7 => OperandType::Indirect(AddressingMode::BX),
_ => unreachable!()
},
ModRM::MOD_1 => {
let disp = memory.read_u8(address + size as u64) as i8;
size += 1;
match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::Indirect(AddressingMode::BX_SI_Disp8(disp)),
ModRM::RM_REG_1 => OperandType::Indirect(AddressingMode::BX_DI_Disp8(disp)),
ModRM::RM_REG_2 => OperandType::Indirect(AddressingMode::BP_SI_Disp8(disp)),
ModRM::RM_REG_3 => OperandType::Indirect(AddressingMode::BP_DI_Disp8(disp)),
ModRM::RM_REG_4 => OperandType::Indirect(AddressingMode::SI_Disp8(disp)),
ModRM::RM_REG_5 => OperandType::Indirect(AddressingMode::DI_Disp8(disp)),
ModRM::RM_REG_6 => OperandType::Indirect(AddressingMode::BP_Disp8(disp)),
ModRM::RM_REG_7 => OperandType::Indirect(AddressingMode::BX_Disp8(disp)),
_ => unreachable!(),
}
},
ModRM::MOD_2 => {
let disp = memory.read_u16(address + size as u64) as i16;
size += 2;
match modrm.unwrap() & ModRM::RM_REG_MASK {
ModRM::RM_REG_0 => OperandType::Indirect(AddressingMode::BX_SI_Disp16(disp)),
ModRM::RM_REG_1 => OperandType::Indirect(AddressingMode::BX_DI_Disp16(disp)),
ModRM::RM_REG_2 => OperandType::Indirect(AddressingMode::BP_SI_Disp16(disp)),
ModRM::RM_REG_3 => OperandType::Indirect(AddressingMode::BP_DI_Disp16(disp)),
ModRM::RM_REG_4 => OperandType::Indirect(AddressingMode::SI_Disp16(disp)),
ModRM::RM_REG_5 => OperandType::Indirect(AddressingMode::DI_Disp16(disp)),
ModRM::RM_REG_6 => OperandType::Indirect(AddressingMode::BP_Disp16(disp)),
ModRM::RM_REG_7 => OperandType::Indirect(AddressingMode::BX_Disp16(disp)),
_ => unreachable!(),
}
},
_ => unreachable!()
}, OperandSize::Word),
OperandFormat::Reg8 => Operand(match modrm.unwrap() & ModRM::REG_MASK {
ModRM::REG_0 => OperandType::AL,
ModRM::REG_1 => OperandType::CL,
ModRM::REG_2 => OperandType::DL,
ModRM::REG_3 => OperandType::BL,
ModRM::REG_4 => OperandType::AH,
ModRM::REG_5 => OperandType::CH,
ModRM::REG_6 => OperandType::DH,
ModRM::REG_7 => OperandType::BH,
_ => unreachable!(),
}, OperandSize::Byte),
OperandFormat::Reg16 => Operand(match modrm.unwrap() & ModRM::REG_MASK {
ModRM::REG_0 => OperandType::AX,
ModRM::REG_1 => OperandType::CX,
ModRM::REG_2 => OperandType::DX,
ModRM::REG_3 => OperandType::BX,
ModRM::REG_4 => OperandType::SP,
ModRM::REG_5 => OperandType::BP,
ModRM::REG_6 => OperandType::SI,
ModRM::REG_7 => OperandType::DI,
_ => unreachable!(),
}, OperandSize::Word),
OperandFormat::Imm8 => {
let op = Operand(OperandType::Imm8(memory.read_u8(address + size as u64)), OperandSize::Byte);
size += 1;
op
},
OperandFormat::Imm16 => {
let op = Operand(OperandType::Imm16(memory.read_u16(address + size as u64)), OperandSize::Word);
size += 2;
op
},
OperandFormat::AL => Operand(OperandType::AL, OperandSize::Byte),
OperandFormat::AX => Operand(OperandType::AX, OperandSize::Word),
OperandFormat::CX => Operand(OperandType::CX, OperandSize::Word),
OperandFormat::DX => Operand(OperandType::DX, OperandSize::Word),
OperandFormat::BX => Operand(OperandType::BX, OperandSize::Word),
OperandFormat::SP => Operand(OperandType::SP, OperandSize::Word),
OperandFormat::BP => Operand(OperandType::BP, OperandSize::Word),
OperandFormat::SI => Operand(OperandType::SI, OperandSize::Word),
OperandFormat::DI => Operand(OperandType::DI, OperandSize::Word),
};
let op1 = match_op(op1ty);
let op2 = match_op(op2ty);
registers.add_ip(size.into());
Self {
opcode,
mnemonic,
op1,
op2,
segment_override,
address,
}
}
}
#[derive(Clone, Copy, Debug)]
pub enum SegmentOverride {
None,
ES,
CS,
SS,
DS,
}
#[non_exhaustive]
#[derive(Clone, Copy, Debug)]
pub enum Mnemonic {
Invalid,
Adc,
Add,
Dec,
Hlt,
Inc,
Nop,
Sbb,
Sub,
Xor,
}
#[derive(Clone, Copy, Debug)]
enum OperandFormat {
NoOperand,
RM8,
RM16,
Reg8,
Reg16,
Imm8,
Imm16,
AL,
AX,
CX,
DX,
BX,
SP,
BP,
SI,
DI,
}
#[derive(Clone, Copy, Debug)]
pub struct Operand(pub OperandType, pub OperandSize);
#[derive(Clone, Copy, Debug)]
pub enum OperandSize {
None,
Byte,
Word,
}
#[derive(Clone, Copy, Debug)]
pub enum OperandType {
NoOperand,
Imm8(u8),
Imm16(u16),
Indirect(AddressingMode),
AL,
AH,
AX,
BL,
BH,
BX,
CL,
CH,
CX,
DL,
DH,
DX,
SI,
DI,
BP,
SP,
IP,
CS,
DS,
ES,
SS,
FLAGS,
}
#[derive(Clone, Copy, Debug)]
#[allow(non_camel_case_types)]
// Indirect addressing modes, using non-camel case names
// read _ as +
pub enum AddressingMode {
// mod 0
BX_SI,
BX_DI,
BP_SI,
BP_DI,
SI,
DI,
Disp16(i16),
BX,
// mod 1
BX_SI_Disp8(i8),
BX_DI_Disp8(i8),
BP_SI_Disp8(i8),
BP_DI_Disp8(i8),
SI_Disp8(i8),
DI_Disp8(i8),
BP_Disp8(i8),
BX_Disp8(i8),
// mod 2
BX_SI_Disp16(i16),
BX_DI_Disp16(i16),
BP_SI_Disp16(i16),
BP_DI_Disp16(i16),
SI_Disp16(i16),
DI_Disp16(i16),
BP_Disp16(i16),
BX_Disp16(i16),
}
bitflags! {
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
struct ModRM: u8 {
const MOD_0 = 0b00000000;
const MOD_1 = 0b01000000;
const MOD_2 = 0b10000000;
const MOD_DIRECT = 0b11000000;
const MOD_MASK = 0b11000000;
const REG_0 = 0b00000000;
const REG_1 = 0b00001000;
const REG_2 = 0b00010000;
const REG_3 = 0b00011000;
const REG_4 = 0b00100000;
const REG_5 = 0b00101000;
const REG_6 = 0b00110000;
const REG_7 = 0b00111000;
const REG_MASK = 0b00111000;
const RM_REG_0 = 0b00000000;
const RM_REG_1 = 0b00000001;
const RM_REG_2 = 0b00000010;
const RM_REG_3 = 0b00000011;
const RM_REG_4 = 0b00000100;
const RM_REG_5 = 0b00000101;
const RM_REG_6 = 0b00000110;
const RM_REG_7 = 0b00000111;
const RM_REG_MASK = 0b00000111;
}
}

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/*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
mod instruction;
mod register;
pub use instruction::*;
pub use register::Registers;
use crate::memory::Memory;
#[derive(Default)]
pub struct Processor {
pub registers: Registers,
pub halted: bool,
}
impl Processor {
pub fn exec(&mut self, memory: &mut Memory, instruction: &Instruction) {
use Mnemonic::*;
match (instruction.mnemonic, instruction.op1.1, instruction.op2.1) {
(Add, OperandSize::Byte, _) => {
let dst = self.operand8(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand8(memory, instruction.op2.0, instruction.segment_override);
let (value, carry) = dst.overflowing_add(src);
// FIXME: AF, PF, OF
self.registers.set_cf(carry);
self.registers.set_sf(value >> 7 != 0);
self.registers.set_zf(value == 0);
self.set_operand8(value, memory, instruction.op1.0, instruction.segment_override);
},
(Add, OperandSize::Word, _) => {
let dst = self.operand16(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand16(memory, instruction.op2.0, instruction.segment_override);
let (value, carry) = dst.overflowing_add(src);
// FIXME: AF, PF, OF
self.registers.set_cf(carry);
self.registers.set_sf(value >> 15 != 0);
self.registers.set_zf(value == 0);
self.set_operand16(value, memory, instruction.op1.0, instruction.segment_override);
},
(Adc, OperandSize::Byte, _) => {
let dst = self.operand8(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand8(memory, instruction.op2.0, instruction.segment_override);
let (value, carry) = dst.carrying_add(src, self.registers.cf());
// FIXME: AF, PF, OF
self.registers.set_cf(carry);
self.registers.set_sf(value >> 7 != 0);
self.registers.set_zf(value == 0);
self.set_operand8(value, memory, instruction.op1.0, instruction.segment_override);
},
(Adc, OperandSize::Word, _) => {
let dst = self.operand16(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand16(memory, instruction.op2.0, instruction.segment_override);
let (value, carry) = dst.carrying_add(src, self.registers.cf());
// FIXME: AF, PF, OF
self.registers.set_cf(carry);
self.registers.set_sf(value >> 15 != 0);
self.registers.set_zf(value == 0);
self.set_operand16(value, memory, instruction.op1.0, instruction.segment_override);
},
(Sbb, OperandSize::Byte, _) => {
let dst = self.operand8(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand8(memory, instruction.op2.0, instruction.segment_override);
let (value, borrow) = dst.borrowing_sub(src, self.registers.cf());
// FIXME: AF, PF, OF
self.registers.set_cf(borrow);
self.registers.set_sf(value >> 7 != 0);
self.registers.set_zf(value == 0);
self.set_operand8(value, memory, instruction.op1.0, instruction.segment_override);
},
(Sbb, OperandSize::Word, _) => {
let dst = self.operand16(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand16(memory, instruction.op2.0, instruction.segment_override);
let (value, borrow) = dst.borrowing_sub(src, self.registers.cf());
// FIXME: AF, PF, OF
self.registers.set_cf(borrow);
self.registers.set_sf(value >> 15 != 0);
self.registers.set_zf(value == 0);
self.set_operand16(value, memory, instruction.op1.0, instruction.segment_override);
},
(Sub, OperandSize::Byte, _) => {
let dst = self.operand8(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand8(memory, instruction.op2.0, instruction.segment_override);
let (value, borrow) = dst.overflowing_sub(src);
// FIXME: AF, PF, OF
self.registers.set_cf(borrow);
self.registers.set_sf(value >> 7 != 0);
self.registers.set_zf(value == 0);
self.set_operand8(value, memory, instruction.op1.0, instruction.segment_override);
},
(Sub, OperandSize::Word, _) => {
let dst = self.operand16(memory, instruction.op1.0, instruction.segment_override);
let src = self.operand16(memory, instruction.op2.0, instruction.segment_override);
let (value, borrow) = dst.overflowing_sub(src);
// FIXME: AF, PF, OF
self.registers.set_cf(borrow);
self.registers.set_sf(value >> 15 != 0);
self.registers.set_zf(value == 0);
self.set_operand16(value, memory, instruction.op1.0, instruction.segment_override);
},
(Inc, OperandSize::Word, _) => {
let dst = self.operand16(memory, instruction.op1.0, instruction.segment_override);
let value = dst.wrapping_add(1);
// FIXME: AF, PF, OF
// preserves CF
self.registers.set_sf(value >> 15 != 0);
self.registers.set_zf(value == 0);
self.set_operand16(value, memory, instruction.op1.0, instruction.segment_override);
},
(Dec, OperandSize::Word, _) => {
let dst = self.operand16(memory, instruction.op1.0, instruction.segment_override);
let value = dst.wrapping_sub(1);
// FIXME: AF, PF, OF
// preserves CF
self.registers.set_sf(value >> 15 != 0);
self.registers.set_zf(value == 0);
self.set_operand16(value, memory, instruction.op1.0, instruction.segment_override);
},
(Nop, _, _) => {},
(Hlt, _, _) => self.halted = true,
_ => unimplemented!("instruction {instruction:?} not implemented"),
}
}
fn operand8(&self, memory: &Memory, operand: OperandType, segment: SegmentOverride) -> u8 {
match operand {
OperandType::Imm8(val) => val,
OperandType::Indirect(mode) => memory.read_u8(self.effective_address(mode, segment)),
OperandType::AL => self.registers.al(),
OperandType::AH => self.registers.ah(),
OperandType::BL => self.registers.bl(),
OperandType::BH => self.registers.bh(),
OperandType::CL => self.registers.cl(),
OperandType::CH => self.registers.ch(),
OperandType::DL => self.registers.dl(),
OperandType::DH => self.registers.dh(),
_ => unreachable!(),
}
}
fn set_operand8(&mut self, val: u8, memory: &mut Memory, operand: OperandType, segment: SegmentOverride) {
match operand {
OperandType::Indirect(mode) => memory.write_u8(self.effective_address(mode, segment), val),
OperandType::AL => self.registers.set_al(val),
OperandType::AH => self.registers.set_ah(val),
OperandType::BL => self.registers.set_bl(val),
OperandType::BH => self.registers.set_bh(val),
OperandType::CL => self.registers.set_cl(val),
OperandType::CH => self.registers.set_ch(val),
OperandType::DL => self.registers.set_dl(val),
OperandType::DH => self.registers.set_dh(val),
_ => unreachable!(),
}
}
fn operand16(&self, memory: &Memory, operand: OperandType, segment: SegmentOverride) -> u16 {
match operand {
OperandType::Imm16(val) => val,
OperandType::Indirect(mode) => memory.read_u16(self.effective_address(mode, segment)),
OperandType::AX => self.registers.ax(),
OperandType::BX => self.registers.bx(),
OperandType::CX => self.registers.cx(),
OperandType::DX => self.registers.dx(),
OperandType::SP => self.registers.sp(),
OperandType::BP => self.registers.bp(),
OperandType::SI => self.registers.si(),
OperandType::DI => self.registers.di(),
_ => unreachable!(),
}
}
fn set_operand16(&mut self, value: u16, memory: &mut Memory, operand: OperandType, segment: SegmentOverride) {
match operand {
OperandType::Indirect(mode) => memory.write_u16(self.effective_address(mode, segment), value),
OperandType::AX => self.registers.set_ax(value),
OperandType::BX => self.registers.set_bx(value),
OperandType::CX => self.registers.set_cx(value),
OperandType::DX => self.registers.set_dx(value),
OperandType::SP => self.registers.set_sp(value),
OperandType::BP => self.registers.set_bp(value),
OperandType::SI => self.registers.set_si(value),
OperandType::DI => self.registers.set_di(value),
_ => unreachable!(),
}
}
fn effective_address(&self, mode: AddressingMode, segment: SegmentOverride) -> u64 {
use AddressingMode::*;
let offset = match mode {
BX_SI => self.registers.bx().wrapping_add(self.registers.si()),
BX_DI => self.registers.bx().wrapping_add(self.registers.di()),
BP_SI => self.registers.bp().wrapping_add(self.registers.si()),
BP_DI => self.registers.bp().wrapping_add(self.registers.di()),
SI => self.registers.si(),
DI => self.registers.di(),
Disp16(disp) => disp as u16,
BX => self.registers.bx(),
BX_SI_Disp8(disp) => self.registers.bx()
.wrapping_add(self.registers.si())
.wrapping_add_signed(disp as i16),
BX_DI_Disp8(disp) => self.registers.bx()
.wrapping_add(self.registers.di())
.wrapping_add_signed(disp as i16),
BP_SI_Disp8(disp) => self.registers.bp()
.wrapping_add(self.registers.si())
.wrapping_add_signed(disp as i16),
BP_DI_Disp8(disp) => self.registers.bp()
.wrapping_add(self.registers.di())
.wrapping_add_signed(disp as i16),
SI_Disp8(disp) => self.registers.si().wrapping_add_signed(disp as i16),
DI_Disp8(disp) => self.registers.di().wrapping_add_signed(disp as i16),
BP_Disp8(disp) => self.registers.bp().wrapping_add_signed(disp as i16),
BX_Disp8(disp) => self.registers.bx().wrapping_add_signed(disp as i16),
BX_SI_Disp16(disp) => self.registers.bx()
.wrapping_add(self.registers.si())
.wrapping_add_signed(disp),
BX_DI_Disp16(disp) => self.registers.bx()
.wrapping_add(self.registers.di())
.wrapping_add_signed(disp),
BP_SI_Disp16(disp) => self.registers.bp()
.wrapping_add(self.registers.si())
.wrapping_add_signed(disp),
BP_DI_Disp16(disp) => self.registers.bp()
.wrapping_add(self.registers.di())
.wrapping_add_signed(disp),
SI_Disp16(disp) => self.registers.si().wrapping_add_signed(disp),
DI_Disp16(disp) => self.registers.di().wrapping_add_signed(disp),
BP_Disp16(disp) => self.registers.bp().wrapping_add_signed(disp),
BX_Disp16(disp) => self.registers.bx().wrapping_add_signed(disp),
};
(match segment {
SegmentOverride::ES => self.registers.es(),
SegmentOverride::CS => self.registers.cs(),
SegmentOverride::SS => self.registers.ss(),
SegmentOverride::DS | SegmentOverride::None => self.registers.ds(),
} as u64) << 4 + offset as u64
}
// fn rm8(&self, memory: &mut Memory, modrm: ModRM, displacement: u16) -> u8 {
// match modrm & ModRM::MOD_MASK {
// ModRM::MOD_DIRECT => self.registers.rm8_gp(modrm),
// ModRM::MOD_0 => memory.read_u8(match modrm & ModRM::RM_REG_MASK {
// ModRM::RM_REG_0 => self.registers.bx() + self.registers.si(),
// ModRM::RM_REG_1 => self.registers.bx() + self.registers.di(),
// ModRM::RM_REG_2 => self.registers.bp() + self.registers.si(),
// ModRM::RM_REG_3 => self.registers.bp() + self.registers.di(),
// ModRM::RM_REG_4 => self.registers.si(),
// ModRM::RM_REG_5 => self.registers.di(),
// ModRM::RM_REG_7 => self.registers.bx(),
// _ => unreachable!(),
// }.into()),
// _ => unimplemented!("register-indirect addressing modes are not implemented"),
// }
// }
// fn r8(&self, memory: &mut Memory, modrm: ModRM) -> u8 {
// match modrm & ModRM::MOD_MASK {
// ModRM::MOD_DIRECT => self.registers.r8_gp(modrm),
// ModRM::MOD_0 => memory.read_u8(match modrm & ModRM::REG_MASK {
// ModRM::REG_0 => self.registers.bx() + self.registers.si(),
// ModRM::REG_1 => self.registers.bx() + self.registers.di(),
// ModRM::REG_2 => self.registers.bp() + self.registers.si(),
// ModRM::REG_3 => self.registers.bp() + self.registers.di(),
// ModRM::REG_4 => self.registers.si(),
// ModRM::REG_5 => self.registers.di(),
// ModRM::REG_7 => self.registers.bx(),
// _ => unreachable!(),
// }.into()),
// _ => unimplemented!("register-indirect addressing modes are not implemented"),
// }
// }
}

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/*
* This Source Code Form is subject to the terms of the Mozilla Public
* License, v. 2.0. If a copy of the MPL was not distributed with this
* file, You can obtain one at https://mozilla.org/MPL/2.0/.
*/
use std::fmt;
pub struct Registers {
ax: u16,
bx: u16,
cx: u16,
dx: u16,
si: u16,
di: u16,
bp: u16,
sp: u16,
ip: u16,
cs: u16,
ds: u16,
es: u16,
ss: u16,
flags: u16,
}
impl Registers {
pub fn dump(&self) {
eprintln!("{}", self);
}
pub fn ax(&self) -> u16 {
self.ax
}
pub fn set_ax(&mut self, value: u16) {
self.ax = value;
}
pub fn al(&self) -> u8 {
self.ax as u8
}
pub fn set_al(&mut self, value: u8) {
self.ax = (self.ax & 0xFF00) | value as u16;
}
pub fn ah(&self) -> u8 {
self.ax.to_le_bytes()[1]
}
pub fn set_ah(&mut self, value: u8) {
self.ax = (self.ax & 0x00FF) | (value as u16) << 8;
}
pub fn bx(&self) -> u16 {
self.bx
}
pub fn set_bx(&mut self, value: u16) {
self.bx = value;
}
pub fn bl(&self) -> u8 {
self.bx as u8
}
pub fn set_bl(&mut self, value: u8) {
self.bx = (self.bx & 0xFF00) | value as u16;
}
pub fn bh(&self) -> u8 {
self.bx.to_le_bytes()[1]
}
pub fn set_bh(&mut self, value: u8) {
self.bx = (self.bx & 0x00FF) | (value as u16) << 8;
}
pub fn cx(&self) -> u16 {
self.cx
}
pub fn set_cx(&mut self, value: u16) {
self.cx = value;
}
pub fn cl(&self) -> u8 {
self.cx as u8
}
pub fn set_cl(&mut self, value: u8) {
self.cx = (self.cx & 0xFF00) | value as u16;
}
pub fn ch(&self) -> u8 {
self.cx.to_le_bytes()[1]
}
pub fn set_ch(&mut self, value: u8) {
self.cx = (self.cx & 0x00FF) | (value as u16) << 8;
}
pub fn dx(&self) -> u16 {
self.dx
}
pub fn set_dx(&mut self, value: u16) {
self.dx = value;
}
pub fn dl(&self) -> u8 {
self.dx as u8
}
pub fn set_dl(&mut self, value: u8) {
self.dx = (self.dx & 0xFF00) | value as u16;
}
pub fn dh(&self) -> u8 {
self.dx.to_le_bytes()[1]
}
pub fn set_dh(&mut self, value: u8) {
self.dx = (self.dx & 0x00FF) | (value as u16) << 8;
}
pub fn si(&self) -> u16 {
self.si
}
pub fn set_si(&mut self, value: u16) {
self.si = value;
}
pub fn di(&self) -> u16 {
self.di
}
pub fn set_di(&mut self, value: u16) {
self.di = value;
}
pub fn bp(&self) -> u16 {
self.bp
}
pub fn set_bp(&mut self, value: u16) {
self.bp = value;
}
pub fn sp(&self) -> u16 {
self.sp
}
pub fn set_sp(&mut self, value: u16) {
self.sp = value;
}
pub fn ip(&self) -> u16 {
self.ip
}
pub fn set_ip(&mut self, value: u16) {
self.ip = value;
}
pub fn add_ip(&mut self, value: i16) {
self.ip = self.ip.wrapping_add_signed(value);
}
pub fn cs(&self) -> u16 {
self.cs
}
pub fn set_cs(&mut self, value: u16) {
self.cs = value;
}
pub fn ds(&self) -> u16 {
self.ds
}
pub fn set_ds(&mut self, value: u16) {
self.ds = value;
}
pub fn es(&self) -> u16 {
self.es
}
pub fn set_es(&mut self, value: u16) {
self.es = value;
}
pub fn ss(&self) -> u16 {
self.ss
}
pub fn set_ss(&mut self, value: u16) {
self.ss = value;
}
pub fn flags(&self) -> u16 {
self.flags
}
pub fn set_flags(&mut self, value: u16) {
self.flags = value;
}
pub fn cf(&self) -> bool {
(self.flags & 1) != 0
}
pub fn set_cf(&mut self, value: bool) {
if value {
self.flags |= 1;
} else {
self.flags &= !1;
}
}
pub fn pf(&self) -> bool {
(self.flags & (1 << 2)) != 0
}
pub fn set_pf(&mut self, value: bool) {
if value {
self.flags |= 1 << 2;
} else {
self.flags &= !(1 << 2);
}
}
pub fn af(&self) -> bool {
(self.flags & (1 << 4)) != 0
}
pub fn set_af(&mut self, value: bool) {
if value {
self.flags |= 1 << 4;
} else {
self.flags &= !(1 << 4);
}
}
pub fn zf(&self) -> bool {
(self.flags & (1 << 6)) != 0
}
pub fn set_zf(&mut self, value: bool) {
if value {
self.flags |= 1 << 6;
} else {
self.flags &= !(1 << 6);
}
}
pub fn sf(&self) -> bool {
(self.flags & (1 << 7)) != 0
}
pub fn set_sf(&mut self, value: bool) {
if value {
self.flags |= 1 << 7;
} else {
self.flags &= !(1 << 7);
}
}
pub fn tf(&self) -> bool {
(self.flags & (1u16 << 8)) != 0
}
pub fn set_tf(&mut self, value: bool) {
if value {
self.flags |= 1 << 8;
} else {
self.flags &= !(1 << 8);
}
}
pub fn r#if(&self) -> bool {
(self.flags & (1 << 9)) != 0
}
pub fn set_if(&mut self, value: bool) {
if value {
self.flags |= 1 << 9;
} else {
self.flags &= !(1 << 9);
}
}
pub fn df(&self) -> bool {
(self.flags & (1 << 10)) != 0
}
pub fn set_df(&mut self, value: bool) {
if value {
self.flags |= 1 << 10;
} else {
self.flags &= !(1 << 10);
}
}
pub fn of(&self) -> bool {
(self.flags & (1 << 11)) != 0
}
pub fn set_of(&mut self, value: bool) {
if value {
self.flags |= 1 << 11;
} else {
self.flags &= !(1 << 11);
}
}
// pub fn sreg(&self, modrm: ModRM) -> u16 {
// match modrm & ModRM::REG_MASK {
// ModRM::REG_0 => self.es(),
// ModRM::REG_1 => self.cs(),
// ModRM::REG_2 => self.ss(),
// ModRM::REG_3 => self.ds(),
// // 8086 doesn't have FS or GS
// // ModRM::REG_4 => self.fs(),
// // ModRM::REG_5 => self.gs(),
// _ => unimplemented!("invalid segment register"),
// }
// }
// pub fn set_sreg(&mut self, modrm: ModRM, value: u16) {
// match modrm & ModRM::REG_MASK {
// ModRM::REG_0 => self.set_es(value),
// ModRM::REG_1 => self.set_cs(value),
// ModRM::REG_2 => self.set_ss(value),
// ModRM::REG_3 => self.set_ds(value),
// // 8086 doesn't have FS or GS
// // ModRM::REG_4 => self.set_fs(value),
// // ModRM::REG_5 => self.set_gs(value),
// _ => unimplemented!("invalid segment register"),
// }
// }
}
impl fmt::Display for Registers {
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
write!(f, "AX: 0x{:x} ", self.ax())?;
write!(f, "BX: 0x{:x} ", self.bx())?;
write!(f, "CX: 0x{:x} ", self.cx())?;
writeln!(f, "DX: 0x{:x}", self.dx())?;
write!(f, "SI: 0x{:x} ", self.si())?;
write!(f, "DI: 0x{:x} ", self.di())?;
write!(f, "BP: 0x{:x} ", self.bp())?;
writeln!(f, "SP: 0x{:x}", self.sp())?;
write!(f, "CS: 0x{:x} ", self.cs())?;
write!(f, "DS: 0x{:x} ", self.ds())?;
write!(f, "ES: 0x{:x} ", self.es())?;
writeln!(f, "SS: 0x{:x}", self.ss())?;
write!(f, "IP: 0x{:x} ", self.ip())?;
write!(f, "FLAGS: 0b{:b}", self.flags())
}
}
impl Default for Registers {
fn default() -> Self {
Self {
ax: 0,
bx: 0,
cx: 0,
dx: 0,
si: 0,
di: 0,
bp: 0,
sp: 0,
ip: 0xFFF0u16,
cs: 0xF000u16,
ds: 0,
es: 0,
ss: 0,
flags: 0x0002u16,
}
}
}