beepo/tests/spmem.v

module spMem(
    output [7:0] dout,
    input clk,
    input oce,
    input ce,
    input reset,
    input wre,
    input [15:0] ad,
    input [7:0] din
);
    reg [0:255] mem = {
        8'h0,
        8'h48, 8'h01, 8'h23,
        8'h48, 8'h02, 8'h46,
        8'h03, 8'h01, 8'h01, 8'h02,
        168'h0
    };

    reg [7:0] r_out;

    assign dout = r_out;

    always @(negedge clk) begin
        r_out <= mem[ad*8+:8];
    end
endmodule