diff --git a/.gitignore b/.gitignore
index 32ee739..4924660 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,5 @@
 impl/
-**/*.gprj
+**/*.gprj*
 tests/*.vcd
 tests/out
 src/gowin_*/
\ No newline at end of file
diff --git a/src/beepo.v b/src/beepo.v
index 3d193c1..f59bac5 100644
--- a/src/beepo.v
+++ b/src/beepo.v
@@ -1,4 +1,4 @@
- `include "instructions.v"
+`include "instructions.v"
 
 module Beepo #(
     parameter FREQ = 27_000_000, 
@@ -89,8 +89,10 @@ module Beepo #(
                     `TX:    r_arg_types_packed = `TX_ARGS;
                     `NOP:   r_arg_types_packed = `NOP_ARGS;
                     `ADD8:  r_arg_types_packed = `ADD8_ARGS;
+                    `ADD16: r_arg_types_packed = `ADD16_ARGS;
                     `ADDI8: r_arg_types_packed = `ADDI8_ARGS;
                     `LI8:   r_arg_types_packed = `LI8_ARGS;
+                    `LI16:  r_arg_types_packed = `LI16_ARGS;
                     default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
                 endcase
 
@@ -167,8 +169,10 @@ module Beepo #(
                     `TX:    r_state <= DONE;
                     `NOP:   ;
                     `ADD8:  set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]);
+                    `ADD16: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][15:0]);
                     `ADDI8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[7:0]);
                     `LI8:   set_register(r_arg_regs[0], r_arg_imm);
+                    `LI16:  set_register(r_arg_regs[0], r_arg_imm);
                 endcase
 
 //                r_tx_send_ctrl[0] <= ~r_tx_send_ctrl[0];
@@ -201,7 +205,7 @@ module Beepo #(
 
     Multi7 display (
         .i_clk(i_clk),
-        .i_hex({r_registers[1][7:0], r_registers[2][7:0]}),
+        .i_hex({r_registers[1][15:0]}),
         .o_segments_drive(o_segments_drive),
         .o_displays_neg(o_displays_neg)
     );
diff --git a/src/instructions.v b/src/instructions.v
index 44bd25c..3723c44 100644
--- a/src/instructions.v
+++ b/src/instructions.v
@@ -11,6 +11,8 @@
 // Binary register-register operations
 `define ADD8    'h03
 `define ADD8_ARGS   {ARG_R, ARG_R, ARG_R, ARG_N}
+`define ADD16   'h04
+`define ADD16_ARGS  {ARG_R, ARG_R, ARG_R, ARG_N}
 
 // Merged divide-remainder
 `define DIRU8   'h20
@@ -32,6 +34,8 @@
 // Load immediate
 `define LI8     'h48
 `define LI8_ARGS    {ARG_R, ARG_B, ARG_N, ARG_N}
+`define LI16    'h49
+`define LI16_ARGS   {ARG_R, ARG_H, ARG_N, ARG_N}
 
 // Conditional jump
 `define JEQ     'h56
\ No newline at end of file
diff --git a/src/programs/add16.mi b/src/programs/add16.mi
new file mode 100644
index 0000000..00a31ab
--- /dev/null
+++ b/src/programs/add16.mi
@@ -0,0 +1,35 @@
+#File_format=Bin
+#Address_depth=32
+#Data_width=8
+00000000
+01001001
+00000001
+00100011
+01000110
+01001001
+00000010
+01000110
+00100011
+00000011
+00000001
+00000001
+00000010
+00000001
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
+00000000
diff --git a/tests/spmem.v b/tests/spmem.v
index ba7229e..bfce47a 100644
--- a/tests/spmem.v
+++ b/tests/spmem.v
@@ -10,11 +10,11 @@ module spMem(
 );
     reg [0:255] mem = {
         8'h0,
-        8'h48, 8'h01, 8'h23,
-        8'h48, 8'h02, 8'h46,
+        8'h49, 8'h01, 8'h23, 8'h46,
+        8'h49, 8'h02, 8'h46, 8'h23,
         8'h03, 8'h01, 8'h01, 8'h02,
         8'h01,
-        160'h0
+        144'h0
     };
 
     reg [7:0] r_out;