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dont work on real hardware

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Bee 2023-11-15 15:46:27 -05:00
parent 2bebf3a9ed
commit 032f0ebc6c
5 changed files with 47 additions and 65534 deletions
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8
holeybeepo.gprj.user
View file

@ -3,9 +3,9 @@
<UserConfig> <UserConfig>
<Version>1.0</Version> <Version>1.0</Version>
<FlowState> <FlowState>
<Process ID="Synthesis" State="4"/> <Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="4"/> <Process ID="Pnr" State="2"/>
<Process ID="Gao" State="4"/> <Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/> <Process ID="Rtl_Gao" State="2"/>
</FlowState> </FlowState>
<ResultFileList> <ResultFileList>
@ -20,5 +20,5 @@
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/holeybeepo_syn.rpt.html"/> <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/holeybeepo_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/holeybeepo_syn_rsc.xml"/> <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/holeybeepo_syn_rsc.xml"/>
</ResultFileList> </ResultFileList>
<Ui>000000ff00000001fd00000002000000000000010000000250fc0200000001fc00000038000002500000000000fffffffaffffffff0200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc00000000000007760000000000fffffffaffffffff0100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000000006700000025000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui> <Ui>000000ff00000001fd000000020000000000000100000002cafc0200000001fc00000038000002ca0000008a01000018fa000000020200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff000000000000000000000670000002ca00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000</Ui>
</UserConfig> </UserConfig>

34
src/beepo.v
View file

@ -1,4 +1,4 @@
// `include "instructions.v" `include "instructions.v"
module Beepo #( module Beepo #(
parameter FREQ = 27_000_000 parameter FREQ = 27_000_000
@ -12,6 +12,7 @@ module Beepo #(
localparam FETCHI = 1; // Instruction is fetched, start fetching first argument localparam FETCHI = 1; // Instruction is fetched, start fetching first argument
localparam FETCHA = 2; // Argument byte is fetched localparam FETCHA = 2; // Argument byte is fetched
localparam EXEC = 3; // Start running localparam EXEC = 3; // Start running
localparam DONE = 7; // Done executing
// Argument types // Argument types
localparam [3:0] ARG_R = 0; // Register localparam [3:0] ARG_R = 0; // Register
@ -30,11 +31,13 @@ module Beepo #(
localparam NUM_REGS = 4; localparam NUM_REGS = 4;
reg [2:0] r_state = IDLE; reg [2:0] r_state = IDLE;
reg r_fetching = 0; // counter for waiting before reading from memory
reg [63:0] r_tick = 0; reg [63:0] r_tick = 0;
// UART tx // UART tx
reg [7:0] r_tx_data = 0; reg [7:0] r_tx_data = 0;
reg r_tx_send = 1; reg [1:0] r_tx_block_ctrl = 2'b0;
reg r_tx_block = 0;
wire w_tx_ready; wire w_tx_ready;
// Registers // Registers
@ -54,6 +57,7 @@ module Beepo #(
reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument
wire [7:0] w_mem_fetch; wire [7:0] w_mem_fetch;
wire w_tx_send = w_tx_ready && r_tx_block;
genvar i; genvar i;
@ -63,15 +67,16 @@ module Beepo #(
end end
endgenerate endgenerate
always @(r_registers[1]) r_tx_data <= r_registers[1]; always @(r_tx_block_ctrl) r_tx_block <= r_tx_block_ctrl[0] ^ r_tx_block_ctrl[1];
always @(posedge i_clk) r_tick <= r_tick + 1; always @(posedge i_clk) r_tick <= r_tick + 1;
always @(posedge i_clk) begin always @(posedge i_clk) begin
case (r_state) if (r_fetching) r_fetching <= r_fetching + 1;
else if (r_tx_block == 0) case (r_state)
IDLE: begin IDLE: begin
r_pc_latch = r_pc; r_pc_latch <= r_pc;
r_pc = r_pc + 1; r_pc <= r_pc + 1;
r_fetching <= 1;
r_state <= FETCHI; r_state <= FETCHI;
end end
FETCHI: begin FETCHI: begin
@ -80,6 +85,7 @@ module Beepo #(
r_arg_bit <= 0; r_arg_bit <= 0;
case (w_mem_fetch) case (w_mem_fetch)
`TX: r_arg_types_packed = `TX_ARGS;
`ADD8: r_arg_types_packed = `ADD8_ARGS; `ADD8: r_arg_types_packed = `ADD8_ARGS;
`LI8: r_arg_types_packed = `LI8_ARGS; `LI8: r_arg_types_packed = `LI8_ARGS;
default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N}; default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
@ -89,6 +95,8 @@ module Beepo #(
r_state <= FETCHA; r_state <= FETCHA;
r_pc_latch <= r_pc; r_pc_latch <= r_pc;
r_pc <= r_pc + 1; r_pc <= r_pc + 1;
r_fetching <= 1;
r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]+:4]; r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]+:4];
r_arg_current_type <= r_arg_types_packed[15:12]; r_arg_current_type <= r_arg_types_packed[15:12];
@ -121,6 +129,7 @@ module Beepo #(
r_pc_latch <= r_pc; r_pc_latch <= r_pc;
r_pc <= r_pc + 1; r_pc <= r_pc + 1;
r_fetching <= 1;
r_arg_bytes = r_arg_bytes - 1; r_arg_bytes = r_arg_bytes - 1;
r_arg_bit <= r_arg_bit + 8; r_arg_bit <= r_arg_bit + 8;
@ -150,15 +159,20 @@ module Beepo #(
end end
EXEC: begin EXEC: begin
case (r_instr) case (r_instr)
`TX: r_state <= DONE;
`ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]); `ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]);
`LI8: set_register(r_arg_regs[0], r_arg_imm); `LI8: set_register(r_arg_regs[0], r_arg_imm);
endcase endcase
r_state <= FETCHI; r_state <= FETCHI;
r_tx_data <= r_registers[1][7:0];
r_tx_block_ctrl[0] <= ~r_tx_block_ctrl[0];
end end
endcase endcase
end end
always @(posedge w_tx_ready) r_tx_block_ctrl[1] <= ~r_tx_block_ctrl[1];
task automatic set_register( task automatic set_register(
input [7:0] being_set, input [7:0] being_set,
input [63:0] setting_to input [63:0] setting_to
@ -167,13 +181,13 @@ module Beepo #(
endtask endtask
uart_tx #( uart_tx #(
.CLK_FRE(FREQ / 1_000_000), .CLK_FRE(FREQ),
.BAUD_RATE(115200) .BAUD_RATE(1000000)
) tx ( ) tx (
.clk(i_clk), .clk(i_clk),
.rst_n(1'b1), .rst_n(1'b1),
.tx_data(r_tx_data), .tx_data(r_tx_data),
.tx_data_valid(r_tx_send), .tx_data_valid(w_tx_send),
.tx_data_ready(w_tx_ready), .tx_data_ready(w_tx_ready),
.tx_pin(o_uart_tx) .tx_pin(o_uart_tx)
); );

65506
src/first.mi
View file

File diff suppressed because it is too large Load diff

2
src/instructions.v
View file

@ -3,6 +3,8 @@
// Program execution control // Program execution control
`define UN 'h00 `define UN 'h00
`define UN_ARGS {ARG_N, ARG_N, ARG_N, ARG_N} `define UN_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
`define TX 'h01
`define TX_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
// Binary register-register operations // Binary register-register operations
`define ADD8 'h03 `define ADD8 'h03

1
tests/spmem.v
View file

@ -13,6 +13,7 @@ module spMem(
8'h48, 8'h01, 8'h23, 8'h48, 8'h01, 8'h23,
8'h48, 8'h02, 8'h46, 8'h48, 8'h02, 8'h46,
8'h03, 8'h01, 8'h01, 8'h02, 8'h03, 8'h01, 8'h01, 8'h02,
8'h01,
168'h0 168'h0
}; };