dont work on real hardware
This commit is contained in:
parent
2bebf3a9ed
commit
032f0ebc6c
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@ -3,9 +3,9 @@
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<UserConfig>
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<Version>1.0</Version>
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<FlowState>
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<Process ID="Synthesis" State="4"/>
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<Process ID="Pnr" State="4"/>
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<Process ID="Gao" State="4"/>
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<Process ID="Synthesis" State="2"/>
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<Process ID="Pnr" State="2"/>
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<Process ID="Gao" State="2"/>
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<Process ID="Rtl_Gao" State="2"/>
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</FlowState>
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<ResultFileList>
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@ -20,5 +20,5 @@
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<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/holeybeepo_syn.rpt.html"/>
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<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/holeybeepo_syn_rsc.xml"/>
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</ResultFileList>
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<Ui>000000ff00000001fd00000002000000000000010000000250fc0200000001fc00000038000002500000000000fffffffaffffffff0200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc00000000000007760000000000fffffffaffffffff0100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000000006700000025000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
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<Ui>000000ff00000001fd000000020000000000000100000002cafc0200000001fc00000038000002ca0000008a01000018fa000000020200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff000000000000000000000670000002ca00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000</Ui>
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</UserConfig>
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34
src/beepo.v
34
src/beepo.v
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@ -1,4 +1,4 @@
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// `include "instructions.v"
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`include "instructions.v"
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module Beepo #(
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parameter FREQ = 27_000_000
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@ -12,6 +12,7 @@ module Beepo #(
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localparam FETCHI = 1; // Instruction is fetched, start fetching first argument
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localparam FETCHA = 2; // Argument byte is fetched
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localparam EXEC = 3; // Start running
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localparam DONE = 7; // Done executing
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// Argument types
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localparam [3:0] ARG_R = 0; // Register
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@ -30,11 +31,13 @@ module Beepo #(
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localparam NUM_REGS = 4;
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reg [2:0] r_state = IDLE;
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reg r_fetching = 0; // counter for waiting before reading from memory
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reg [63:0] r_tick = 0;
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// UART tx
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reg [7:0] r_tx_data = 0;
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reg r_tx_send = 1;
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reg [1:0] r_tx_block_ctrl = 2'b0;
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reg r_tx_block = 0;
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wire w_tx_ready;
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// Registers
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@ -54,6 +57,7 @@ module Beepo #(
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reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument
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wire [7:0] w_mem_fetch;
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wire w_tx_send = w_tx_ready && r_tx_block;
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genvar i;
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@ -63,15 +67,16 @@ module Beepo #(
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end
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endgenerate
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always @(r_registers[1]) r_tx_data <= r_registers[1];
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always @(r_tx_block_ctrl) r_tx_block <= r_tx_block_ctrl[0] ^ r_tx_block_ctrl[1];
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always @(posedge i_clk) r_tick <= r_tick + 1;
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always @(posedge i_clk) begin
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case (r_state)
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if (r_fetching) r_fetching <= r_fetching + 1;
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else if (r_tx_block == 0) case (r_state)
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IDLE: begin
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r_pc_latch = r_pc;
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r_pc = r_pc + 1;
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_fetching <= 1;
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r_state <= FETCHI;
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end
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FETCHI: begin
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r_arg_bit <= 0;
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case (w_mem_fetch)
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`TX: r_arg_types_packed = `TX_ARGS;
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`ADD8: r_arg_types_packed = `ADD8_ARGS;
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`LI8: r_arg_types_packed = `LI8_ARGS;
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default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
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r_state <= FETCHA;
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_fetching <= 1;
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r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]+:4];
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r_arg_current_type <= r_arg_types_packed[15:12];
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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r_fetching <= 1;
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r_arg_bytes = r_arg_bytes - 1;
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r_arg_bit <= r_arg_bit + 8;
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end
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EXEC: begin
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case (r_instr)
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`TX: r_state <= DONE;
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`ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]);
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`LI8: set_register(r_arg_regs[0], r_arg_imm);
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endcase
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r_state <= FETCHI;
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r_tx_data <= r_registers[1][7:0];
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r_tx_block_ctrl[0] <= ~r_tx_block_ctrl[0];
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end
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endcase
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end
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always @(posedge w_tx_ready) r_tx_block_ctrl[1] <= ~r_tx_block_ctrl[1];
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task automatic set_register(
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input [7:0] being_set,
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input [63:0] setting_to
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endtask
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uart_tx #(
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.CLK_FRE(FREQ / 1_000_000),
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.BAUD_RATE(115200)
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.CLK_FRE(FREQ),
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.BAUD_RATE(1000000)
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) tx (
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.clk(i_clk),
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.rst_n(1'b1),
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.tx_data(r_tx_data),
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.tx_data_valid(r_tx_send),
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.tx_data_valid(w_tx_send),
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.tx_data_ready(w_tx_ready),
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.tx_pin(o_uart_tx)
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);
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65506
src/first.mi
65506
src/first.mi
File diff suppressed because it is too large
Load diff
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// Program execution control
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`define UN 'h00
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`define UN_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
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`define TX 'h01
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`define TX_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
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// Binary register-register operations
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`define ADD8 'h03
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@ -13,6 +13,7 @@ module spMem(
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8'h48, 8'h01, 8'h23,
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8'h48, 8'h02, 8'h46,
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8'h03, 8'h01, 8'h01, 8'h02,
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8'h01,
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168'h0
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};
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