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@ -7,19 +7,16 @@
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$finish; \
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$finish; \
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end
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end
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module tb_adding(
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module tb_adding();
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output o_uart_tx
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reg clk = 0;
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);
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reg clk = 0;
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Beepo #(
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Beepo #(
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.FREQ(1),
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.FREQ(1),
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.UART_BAUD(1_000_000)
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.UART_BAUD(1_000_000)
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) bep (
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) bep (
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.i_clk(clk),
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.i_clk(clk)
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.o_uart_tx(o_uart_tx)
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);
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);
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localparam CLK_PERIOD = 1.0;
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localparam CLK_PERIOD = 1.0;
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always #(CLK_PERIOD/2) clk=~clk;
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always #(CLK_PERIOD/2) clk=~clk;
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@ -34,7 +31,7 @@ Beepo #(
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);
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);
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end
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end
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// should probably do more tests than just the end
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// should probably do more granular tests
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initial #10000 begin
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initial #10000 begin
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`assert(bep.r_registers[1], 64'h2020202040406090);
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`assert(bep.r_registers[1], 64'h2020202040406090);
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$finish;
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$finish;
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