unger

tests/adding/adding.v

@@ -7,19 +7,16 @@
         $finish; \
     end
 
-module tb_adding(
-    output o_uart_tx
-);
-
+module tb_adding();
     reg clk = 0;
 
     Beepo #(
         .FREQ(1),
         .UART_BAUD(1_000_000)
     ) bep (
-    .i_clk(clk),
-    .o_uart_tx(o_uart_tx)
+        .i_clk(clk)
     );
+
     localparam CLK_PERIOD = 1.0;
     always #(CLK_PERIOD/2) clk=~clk;
 
@@ -34,7 +31,7 @@ Beepo #(
         );
     end
 
-    // should probably do more tests than just the end
+    // should probably do more granular tests
     initial #10000 begin
         `assert(bep.r_registers[1], 64'h2020202040406090);
         $finish;