From 6abbabb7eca0351c20e088dbd962ab0c991bc4f6 Mon Sep 17 00:00:00 2001 From: Bee Date: Wed, 15 Nov 2023 18:44:11 -0500 Subject: [PATCH] addi8 bepobebo --- holeybeepo.gprj.user | 2 +- src/beepo.v | 63 +++---- src/instructions.v | 3 + src/memory.mi | 259 ----------------------------- src/{first.mi => programs/add8.mi} | 0 src/programs/addi8.mi | 35 ++++ tests/beepo.v | 3 +- tests/inputs.txt | 1 + tests/spmem.v | 2 +- 9 files changed, 77 insertions(+), 291 deletions(-) delete mode 100644 src/memory.mi rename src/{first.mi => programs/add8.mi} (100%) create mode 100644 src/programs/addi8.mi diff --git a/holeybeepo.gprj.user b/holeybeepo.gprj.user index 531b4b5..b23e5ed 100644 --- a/holeybeepo.gprj.user +++ b/holeybeepo.gprj.user @@ -20,5 +20,5 @@ - 000000ff00000001fd000000020000000000000100000002cafc0200000001fc00000038000002ca0000008a01000018fa000000000200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff000000000000000000000670000002ca00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000 + 000000ff00000001fd00000002000000000000010000000260fc0200000001fc00000038000002600000008a01000018fa000000000200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000000006700000026000000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000 diff --git a/src/beepo.v b/src/beepo.v index af0e65a..3d193c1 100644 --- a/src/beepo.v +++ b/src/beepo.v @@ -1,7 +1,8 @@ -`include "instructions.v" + `include "instructions.v" module Beepo #( - parameter FREQ = 27_000_000 + parameter FREQ = 27_000_000, + parameter UART_BAUD = 115200 ) ( input i_clk, input i_button1, @@ -37,10 +38,9 @@ module Beepo #( reg [63:0] r_tick = 0; // UART tx - reg [7:0] r_tx_data = 0; - reg [1:0] r_tx_block_ctrl = 2'b0; - reg r_tx_block = 0; - wire w_tx_ready; +// reg [7:0] r_tx_data = 0; +// reg r_tx_reset_n = 1; +// wire w_tx_ready; // Registers reg [63:0] r_pc = PC_START; // program counter @@ -53,13 +53,12 @@ module Beepo #( reg [1:0] r_arg_index = 3; // the instruction index currently being fetched reg [3:0] r_arg_types [0:3]; // the types of each argument to be fetched - reg [15:0] r_arg_types_packed = 0; // to be unpacked into r_arg_types + reg [15:0] r_arg_types_packed = 0; // to be unpacked into r_arg_types reg [2:0] r_arg_bytes = 0; // the number of bytes left to fetch for the current argument reg [3:0] r_arg_current_type = 8; // the type of the current argument reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument wire [7:0] w_mem_fetch; - wire w_tx_send = w_tx_ready && r_tx_block; genvar i; @@ -69,12 +68,12 @@ module Beepo #( end endgenerate - always @(r_tx_block_ctrl) r_tx_block <= r_tx_block_ctrl[0] ^ r_tx_block_ctrl[1]; always @(posedge i_clk) r_tick <= r_tick + 1; + // always @(r_registers[1]) r_tx_data <= r_registers[1]; always @(posedge i_clk) begin if (r_fetching) r_fetching <= r_fetching + 1; - else if (r_tx_block == 0) case (r_state) + else case (r_state) IDLE: begin r_pc_latch <= r_pc; r_pc <= r_pc + 1; @@ -88,7 +87,9 @@ module Beepo #( case (w_mem_fetch) `TX: r_arg_types_packed = `TX_ARGS; + `NOP: r_arg_types_packed = `NOP_ARGS; `ADD8: r_arg_types_packed = `ADD8_ARGS; + `ADDI8: r_arg_types_packed = `ADDI8_ARGS; `LI8: r_arg_types_packed = `LI8_ARGS; default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N}; endcase @@ -99,11 +100,11 @@ module Beepo #( r_pc <= r_pc + 1; r_fetching <= 1; - r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]+:4]; + r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]*4+:4]; r_arg_current_type <= r_arg_types_packed[15:12]; - + r_arg_types[0] <= r_arg_types_packed[15:12]; - r_arg_types[1] <= r_arg_types_packed[11:8]; + r_arg_types[1] <= r_arg_types_packed[11:8]; r_arg_types[2] <= r_arg_types_packed[7:4]; r_arg_types[3] <= r_arg_types_packed[3:0]; @@ -160,39 +161,43 @@ module Beepo #( end end EXEC: begin + r_state <= FETCHI; + case (r_instr) `TX: r_state <= DONE; + `NOP: ; `ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]); + `ADDI8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[7:0]); `LI8: set_register(r_arg_regs[0], r_arg_imm); endcase - r_state <= FETCHI; - r_tx_data <= r_registers[1][7:0]; - r_tx_block_ctrl[0] <= ~r_tx_block_ctrl[0]; +// r_tx_send_ctrl[0] <= ~r_tx_send_ctrl[0]; end endcase end - always @(posedge w_tx_ready) r_tx_block_ctrl[1] <= ~r_tx_block_ctrl[1]; + // always @(posedge i_clk) begin + // if (w_tx_send && w_tx_ready) r_tx_send_ctrl[1] <= r_tx_send_ctrl[0]; + // end task automatic set_register( input [7:0] being_set, input [63:0] setting_to ); - if (being_set != 0) r_registers[being_set] <= setting_to; + if (being_set != 0) r_registers[being_set] = setting_to; endtask - uart_tx #( - .CLK_FRE(FREQ), - .BAUD_RATE(1000000) - ) tx ( - .clk(i_clk), - .rst_n(1'b1), - .tx_data(r_tx_data), - .tx_data_valid(w_tx_send), - .tx_data_ready(w_tx_ready), - .tx_pin(o_uart_tx) - ); + // uart_tx #( + // .CLK_FRE(FREQ / 1_000_000), + // .BAUD_RATE(UART_BAUD) + // ) tx ( + // .clk(i_clk), + // .rst_n(1), + // .tx_data(r_tx_data), + // .tx_data_valid(w_tx_send), + // .tx_data_ready(w_tx_ready), + // .tx_pin(o_uart_tx) + // ); Multi7 display ( .i_clk(i_clk), diff --git a/src/instructions.v b/src/instructions.v index 6cef0da..44bd25c 100644 --- a/src/instructions.v +++ b/src/instructions.v @@ -5,6 +5,8 @@ `define UN_ARGS {ARG_N, ARG_N, ARG_N, ARG_N} `define TX 'h01 `define TX_ARGS {ARG_N, ARG_N, ARG_N, ARG_N} +`define NOP 'h02 +`define NOP_ARGS {ARG_N, ARG_N, ARG_N, ARG_N} // Binary register-register operations `define ADD8 'h03 @@ -19,6 +21,7 @@ // Binary register-immediate operations `define ADDI8 'h2D +`define ADDI8_ARGS {ARG_R, ARG_R, ARG_B, ARG_N} // Register-immediate bitshifts `define SLUI8 'h38 diff --git a/src/memory.mi b/src/memory.mi deleted file mode 100644 index 7400d14..0000000 --- a/src/memory.mi +++ /dev/null @@ -1,259 +0,0 @@ -#File_format=Bin -#Address_depth=256 -#Data_width=8 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -01101001 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00100011 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 diff --git a/src/first.mi b/src/programs/add8.mi similarity index 100% rename from src/first.mi rename to src/programs/add8.mi diff --git a/src/programs/addi8.mi b/src/programs/addi8.mi new file mode 100644 index 0000000..a6467af --- /dev/null +++ b/src/programs/addi8.mi @@ -0,0 +1,35 @@ +#File_format=Bin +#Address_depth=32 +#Data_width=8 +00000000 +01001000 +00000001 +00100011 +00101101 +00000001 +00000001 +10000111 +00000001 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/tests/beepo.v b/tests/beepo.v index aff2ff2..6ae1632 100644 --- a/tests/beepo.v +++ b/tests/beepo.v @@ -8,7 +8,8 @@ module tb_beepo( reg clk = 0; Beepo #( - .FREQ(1) + .FREQ(1), + .UART_BAUD(1_000_000) ) bep ( .i_clk(clk), .o_uart_tx(o_uart_tx) diff --git a/tests/inputs.txt b/tests/inputs.txt index d27ae6d..f2da68e 100644 --- a/tests/inputs.txt +++ b/tests/inputs.txt @@ -1,4 +1,5 @@ ../src/instructions.v beepo.v ../src/uart_tx.v +../src/multi7.v spmem.v diff --git a/tests/spmem.v b/tests/spmem.v index c325ede..ba7229e 100644 --- a/tests/spmem.v +++ b/tests/spmem.v @@ -14,7 +14,7 @@ module spMem( 8'h48, 8'h02, 8'h46, 8'h03, 8'h01, 8'h01, 8'h02, 8'h01, - 168'h0 + 160'h0 }; reg [7:0] r_out;