suhc goop
This commit is contained in:
parent
3a2c675613
commit
8de052939b
1
.gitignore
vendored
1
.gitignore
vendored
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@ -3,3 +3,4 @@ impl/
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tests/**/*.vcd
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tests/**/*.vcd
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tests/**/out
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tests/**/out
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src/gowin_*/
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src/gowin_*/
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**/target/
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5
Makefile
5
Makefile
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@ -1,4 +1,7 @@
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BOARD = tangnano20k
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BOARD = tangnano20k
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flash:
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flash:
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openFPGALoader -m -b ${BOARD} impl/pnr/*.fs
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openFPGALoader -m -b ${BOARD} impl/pnr/holeybeepo.fs
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debug:
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openFPGALoader -m -b ${BOARD} impl/pnr/ao_0.fs
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7
slapper/Cargo.lock
generated
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7
slapper/Cargo.lock
generated
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@ -0,0 +1,7 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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version = 3
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[[package]]
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name = "slapper"
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version = "0.1.0"
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8
slapper/Cargo.toml
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8
slapper/Cargo.toml
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[package]
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name = "slapper"
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version = "0.1.0"
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edition = "2021"
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[dependencies]
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64
slapper/src/main.rs
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64
slapper/src/main.rs
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@ -0,0 +1,64 @@
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use std::{process::exit, path::PathBuf, fs::File, io::{Read, Write}};
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fn main() {
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let from = std::env::args().nth(1).unwrap_or_else(|| {
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println!("You gotta give me a binary file to slap the hex out of");
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exit(1);
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});
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let into = std::env::args().nth(2).unwrap_or_else(|| {
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println!("I need a file to put these values into");
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exit(1);
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});
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let output = std::env::args().nth(3).unwrap_or_else(|| {
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println!("I need a file to output to");
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exit(1);
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});
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let from_path: PathBuf = (&from).into();
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let into_path: PathBuf = (&into).into();
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let output_path: PathBuf = (&output).into();
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let mut from_file = File::open(&from_path).unwrap_or_else(|e| {
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println!("Error opening {from_path:?}: {e}");
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exit(1);
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});
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let mut into_file = File::open(&into_path).unwrap_or_else(|e| {
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println!("Error opening {into_path:?}: {e}");
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exit(1);
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});
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let mut output_file = File::create(&output_path).unwrap_or_else(|e| {
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println!("Error creating {output_path:?}: {e}");
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exit(1);
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});
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let mut from_contents: Vec<u8> = Vec::with_capacity(128);
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let mut into_contents: String = String::with_capacity(1024);
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from_file.read_to_end(&mut from_contents).unwrap_or_else(|e| {
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println!("Failed to read {from_path:?} {e}");
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exit(1);
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});
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into_file.read_to_string(&mut into_contents).unwrap_or_else(|e| {
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println!("Failed to read {into_path:?}: {e}");
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exit(1);
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});
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let mem_value: String = from_contents.iter().map(|byte| {
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format!("{byte:02X}")
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}).collect();
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let bit_length = from_contents.len() * 8;
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let insert_mem = format!("reg [0:{}] mem = {bit_length}'h{mem_value};", bit_length - 1);
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into_contents = into_contents.replace("$$insert_mem$$", &insert_mem);
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output_file.write_all(into_contents.as_bytes()).unwrap_or_else(|e| {
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println!("Failed writing to {output_path:?}: {e}");
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exit(1);
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});
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}
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@ -29,7 +29,7 @@ module Beepo #(
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localparam [0:31] ARG_SIZES = {4'd1, 4'd4, 4'd2, 4'd1, 4'd2, 4'd4, 4'd8, 4'd8};
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localparam [0:31] ARG_SIZES = {4'd1, 4'd4, 4'd2, 4'd1, 4'd2, 4'd4, 4'd8, 4'd8};
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localparam PC_START = 1;
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localparam PC_START = 0;
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localparam NUM_REGS = 4;
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localparam NUM_REGS = 4;
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reg [2:0] r_state = IDLE;
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reg [2:0] r_state = IDLE;
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@ -185,6 +185,8 @@ module Beepo #(
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endcase
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endcase
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end
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end
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task automatic set_register(
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task automatic set_register(
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input [7:0] being_set,
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input [7:0] being_set,
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input [63:0] setting_to
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input [63:0] setting_to
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@ -7,8 +7,8 @@
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//Device Version: C
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//Device Version: C
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//Created Time: Tue 11 14 12:00:04 2023
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//Created Time: Tue 11 14 12:00:04 2023
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IO_LOC "o_uart_tx" 69;
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//IO_LOC "o_uart_tx" 69;
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IO_PORT "o_uart_tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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//IO_PORT "o_uart_tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "i_clk" 4;
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IO_LOC "i_clk" 4;
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IO_PORT "i_clk" PULL_MODE=UP BANK_VCCIO=1.8;
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IO_PORT "i_clk" PULL_MODE=UP BANK_VCCIO=1.8;
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IO_LOC "o_displays_neg[3]" 80;
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IO_LOC "o_displays_neg[3]" 80;
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30
tests/Makefile
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30
tests/Makefile
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ICARUS_FILES = inputs.txt
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# Used in all tests
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build:
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mkdir -p $@
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release/slapper:
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cargo build --manifest-path ../slapper/Cargo.toml -r
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slapper: release/slapper
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cp ../slapper/target/release/slapper $@
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# Addition tests
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build/adding: | build
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mkdir -p $@
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build/adding/program.bin: adding/program.rhai | build/adding
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./hbasm $< > $@
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build/adding/spmem_gen.v: build/adding/program.bin slapper | build/adding
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./slapper $< spmem.v $@
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build/adding/out: ${ICARUS_FILES} build/adding/spmem_gen.v | build/adding
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iverilog -o $@ -c $< -s tb_adding
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build/adding/dump.vcd: build/adding/out | build/adding
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vvp $<
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adding-wave: build/adding/dump.vcd | build/adding
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gtkwave build/adding/dump.vcd
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@ -1,11 +0,0 @@
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ICARUS_FILES = inputs.txt
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ICARUS_OUT = out
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build: ${ICARUS_FILES}
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iverilog -o ${ICARUS_OUT} -c $^ -s tb_adding
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run: build
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vvp ${ICARUS_OUT}
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wave: run
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gtkwave dump.vcd
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1
tests/adding/adding.bin
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1
tests/adding/adding.bin
Normal file
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HIJK-./0
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1
tests/adding/build/adding.bin
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1
tests/adding/build/adding.bin
Normal file
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@ -0,0 +1 @@
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HIJK-./0
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24
tests/adding/build/spmem_gen.v
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24
tests/adding/build/spmem_gen.v
Normal file
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@ -0,0 +1,24 @@
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module spMem(
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output [7:0] dout,
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input clk,
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input oce,
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input ce,
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input reset,
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input wre,
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input [15:0] ad,
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input [7:0] din
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);
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// gets replaced with the memory for the program to run
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reg [0:535] mem = 536'h480110490210104A03101010104B041010101010101010030101010401010205010103060101042D0101102E010110102F010110101010300101101010101010101001;
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reg [15:0] r_ad_prev = 0;
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reg [7:0] r_out;
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assign dout = r_out;
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always @(negedge clk) begin
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// one full clock cycle before being fetched
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if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
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else r_ad_prev = ad;
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end
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endmodule
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7
tests/adding/mem.py
Normal file
7
tests/adding/mem.py
Normal file
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with open("adding.bin", "rb") as f:
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content = f.read()
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length_bits = len(content) * 8
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mash = "".join([hex(int(i))[2:].zfill(2) for i in content])
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shadow = f"reg [0:{length_bits-1}] mem = {length_bits}'h{mash}; // generated"
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print(shadow)
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16
tests/adding/program.rhai
Normal file
16
tests/adding/program.rhai
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@ -0,0 +1,16 @@
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li8 (r1, 0x10);
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li16 (r2, 0x1010);
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li32 (r3, 0x10101010);
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li64 (r4, 0x1010101010101010);
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add8 (r1, r1, r1);
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add16 (r1, r1, r2);
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add32 (r1, r1, r3);
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add64 (r1, r1, r4);
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addi8 (r1, r1, 0x10);
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addi16 (r1, r1, 0x1010);
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addi32 (r1, r1, 0x10101010);
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addi64 (r1, r1, 0x1010101010101010);
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tx();
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@ -1,35 +0,0 @@
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module spMem(
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output [7:0] dout,
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input clk,
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input oce,
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input ce,
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input reset,
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input wre,
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input [15:0] ad,
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input [7:0] din
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);
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reg [0:543] mem = {
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8'h0,
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8'h48, 8'h01, 8'h10, // r1 <- 0x10
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8'h49, 8'h02, 16'h1010, // r2 <- 0x1010
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8'h4A, 8'h03, 32'h10101010, // r3 <- 0x10101010
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8'h4B, 8'h04, 64'h1010101010101010, // r4 <- 0x1010101010101010
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8'h03, 8'h01, 8'h01, 8'h01, // r1 <- r1 + r1 (r1 = 0x20)
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8'h04, 8'h01, 8'h01, 8'h02, // r1 <- r1 + r2 (r1 = 0x1030)
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8'h05, 8'h01, 8'h01, 8'h03, // r1 <- r1 + r3 (r1 = 0x10102040)
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8'h06, 8'h01, 8'h01, 8'h04, // r1 <- r1 + r4 (r1 = 0x1010101020203050)
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8'h2D, 8'h01, 8'h01, 8'h10, // r1 <- r1 + 0x10 (r1 = 0x1010101020203060)
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8'h2E, 8'h01, 8'h01, 16'h1010, // r1 <- r1 + 0x1010 (r1 = 0x1010101020204070)
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8'h2F, 8'h01, 8'h01, 32'h10101010, // r1 <- r1 + 0x10101010 (r1 = 0x1010101030305080)
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8'h30, 8'h01, 8'h01, 64'h1010101010101010, // r1 <- r1 + 0x1010101010101010 (r1 = 0x2020202040406090)
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8'h01 // die
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};
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reg [7:0] r_out;
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assign dout = r_out;
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always @(negedge clk) begin
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r_out <= mem[ad*8+:8];
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end
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endmodule
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0
tests/build/adding.bin
Normal file
0
tests/build/adding.bin
Normal file
0
tests/build/adding/program.bin
Normal file
0
tests/build/adding/program.bin
Normal file
24
tests/build/adding/spmem_gen.v
Normal file
24
tests/build/adding/spmem_gen.v
Normal file
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@ -0,0 +1,24 @@
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|
module spMem(
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output [7:0] dout,
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input clk,
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input oce,
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|
input ce,
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input reset,
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|
input wre,
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|
input [15:0] ad,
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|
input [7:0] din
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|
);
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|
// gets replaced with the memory for the program to run
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|
reg [0:18446744073709551615] mem = 0'h;
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|
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|
reg [15:0] r_ad_prev = 0;
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|
reg [7:0] r_out;
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|
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|
assign dout = r_out;
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|
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|
always @(negedge clk) begin
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|
// one full clock cycle before being fetched
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|
if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
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|
else r_ad_prev = ad;
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|
end
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|
endmodule
|
24
tests/build/adding_mem.v
Normal file
24
tests/build/adding_mem.v
Normal file
|
@ -0,0 +1,24 @@
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|
module spMem(
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|
output [7:0] dout,
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|
input clk,
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|
input oce,
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|
input ce,
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|
input reset,
|
||||||
|
input wre,
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||||||
|
input [15:0] ad,
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||||||
|
input [7:0] din
|
||||||
|
);
|
||||||
|
// gets replaced with the memory for the program to run
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|
reg [0:18446744073709551615] mem = 0'h;
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|
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|
reg [15:0] r_ad_prev = 0;
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|
reg [7:0] r_out;
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||||||
|
|
||||||
|
assign dout = r_out;
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|
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||||||
|
always @(negedge clk) begin
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|
// one full clock cycle before being fetched
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||||||
|
if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
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|
else r_ad_prev = ad;
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|
end
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|
endmodule
|
BIN
tests/hbasm
Executable file
BIN
tests/hbasm
Executable file
Binary file not shown.
|
@ -2,4 +2,4 @@
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adding.v
|
adding.v
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../../src/uart_tx.v
|
../../src/uart_tx.v
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../../src/multi7.v
|
../../src/multi7.v
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spmem.v
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../build/adding_mem.v
|
BIN
tests/slapper
Executable file
BIN
tests/slapper
Executable file
Binary file not shown.
24
tests/spmem.v
Normal file
24
tests/spmem.v
Normal file
|
@ -0,0 +1,24 @@
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|
module spMem(
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|
output [7:0] dout,
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|
input clk,
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|
input oce,
|
||||||
|
input ce,
|
||||||
|
input reset,
|
||||||
|
input wre,
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||||||
|
input [15:0] ad,
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||||||
|
input [7:0] din
|
||||||
|
);
|
||||||
|
// gets replaced with the memory for the program to run
|
||||||
|
$$insert_mem$$
|
||||||
|
|
||||||
|
reg [15:0] r_ad_prev = 0;
|
||||||
|
reg [7:0] r_out;
|
||||||
|
|
||||||
|
assign dout = r_out;
|
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|
|
||||||
|
always @(negedge clk) begin
|
||||||
|
// one full clock cycle before being fetched
|
||||||
|
if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
|
||||||
|
else r_ad_prev = ad;
|
||||||
|
end
|
||||||
|
endmodule
|
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