Compare commits
2 commits
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6abbabb7ec
| Author | SHA1 | Date | |
|---|---|---|---|
 Bee
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6abbabb7ec | ||
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Bee
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a1fbfe1188 |
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@ -20,5 +20,5 @@
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|||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/holeybeepo_syn.rpt.html"/>
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<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/holeybeepo_syn_rsc.xml"/>
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</ResultFileList>
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<Ui>000000ff00000001fd000000020000000000000100000002cafc0200000001fc00000038000002ca0000008a01000018fa000000020200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff000000000000000000000670000002ca00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000</Ui>
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<Ui>000000ff00000001fd00000002000000000000010000000260fc0200000001fc00000038000002600000008a01000018fa000000000200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000000006700000026000000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000</Ui>
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</UserConfig>
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72
src/beepo.v
72
src/beepo.v
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@ -1,11 +1,14 @@
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`include "instructions.v"
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`include "instructions.v"
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module Beepo #(
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parameter FREQ = 27_000_000
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parameter FREQ = 27_000_000,
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parameter UART_BAUD = 115200
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) (
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input i_clk,
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input i_button1,
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output o_uart_tx
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output o_uart_tx,
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output [6:0] o_segments_drive,
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output [3:0] o_displays_neg
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);
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// State values
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localparam IDLE = 0; // Start fetching instruction
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@ -35,10 +38,9 @@ module Beepo #(
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reg [63:0] r_tick = 0;
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// UART tx
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reg [7:0] r_tx_data = 0;
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reg [1:0] r_tx_block_ctrl = 2'b0;
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reg r_tx_block = 0;
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wire w_tx_ready;
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// reg [7:0] r_tx_data = 0;
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// reg r_tx_reset_n = 1;
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// wire w_tx_ready;
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// Registers
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reg [63:0] r_pc = PC_START; // program counter
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@ -51,13 +53,12 @@ module Beepo #(
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reg [1:0] r_arg_index = 3; // the instruction index currently being fetched
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reg [3:0] r_arg_types [0:3]; // the types of each argument to be fetched
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reg [15:0] r_arg_types_packed = 0; // to be unpacked into r_arg_types
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reg [15:0] r_arg_types_packed = 0; // to be unpacked into r_arg_types
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reg [2:0] r_arg_bytes = 0; // the number of bytes left to fetch for the current argument
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reg [3:0] r_arg_current_type = 8; // the type of the current argument
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reg [5:0] r_arg_bit = 0; // the current lower bit index being fetched for the current argument
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wire [7:0] w_mem_fetch;
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wire w_tx_send = w_tx_ready && r_tx_block;
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genvar i;
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@ -67,12 +68,12 @@ module Beepo #(
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end
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endgenerate
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always @(r_tx_block_ctrl) r_tx_block <= r_tx_block_ctrl[0] ^ r_tx_block_ctrl[1];
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always @(posedge i_clk) r_tick <= r_tick + 1;
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// always @(r_registers[1]) r_tx_data <= r_registers[1];
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always @(posedge i_clk) begin
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if (r_fetching) r_fetching <= r_fetching + 1;
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else if (r_tx_block == 0) case (r_state)
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else case (r_state)
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IDLE: begin
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r_pc_latch <= r_pc;
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r_pc <= r_pc + 1;
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@ -86,7 +87,9 @@ module Beepo #(
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case (w_mem_fetch)
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`TX: r_arg_types_packed = `TX_ARGS;
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`NOP: r_arg_types_packed = `NOP_ARGS;
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`ADD8: r_arg_types_packed = `ADD8_ARGS;
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`ADDI8: r_arg_types_packed = `ADDI8_ARGS;
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`LI8: r_arg_types_packed = `LI8_ARGS;
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default: r_arg_types_packed = {ARG_N, ARG_N, ARG_N, ARG_N};
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endcase
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@ -97,11 +100,11 @@ module Beepo #(
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r_pc <= r_pc + 1;
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r_fetching <= 1;
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r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]+:4];
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r_arg_bytes <= ARG_SIZES[r_arg_types_packed[15:12]*4+:4];
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r_arg_current_type <= r_arg_types_packed[15:12];
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r_arg_types[0] <= r_arg_types_packed[15:12];
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r_arg_types[1] <= r_arg_types_packed[11:8];
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r_arg_types[1] <= r_arg_types_packed[11:8];
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r_arg_types[2] <= r_arg_types_packed[7:4];
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r_arg_types[3] <= r_arg_types_packed[3:0];
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@ -158,38 +161,49 @@ module Beepo #(
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end
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end
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EXEC: begin
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r_state <= FETCHI;
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case (r_instr)
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`TX: r_state <= DONE;
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`NOP: ;
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`ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]);
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`ADDI8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_arg_imm[7:0]);
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`LI8: set_register(r_arg_regs[0], r_arg_imm);
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endcase
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r_state <= FETCHI;
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r_tx_data <= r_registers[1][7:0];
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r_tx_block_ctrl[0] <= ~r_tx_block_ctrl[0];
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// r_tx_send_ctrl[0] <= ~r_tx_send_ctrl[0];
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end
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endcase
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end
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always @(posedge w_tx_ready) r_tx_block_ctrl[1] <= ~r_tx_block_ctrl[1];
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// always @(posedge i_clk) begin
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// if (w_tx_send && w_tx_ready) r_tx_send_ctrl[1] <= r_tx_send_ctrl[0];
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// end
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task automatic set_register(
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input [7:0] being_set,
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input [63:0] setting_to
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);
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if (being_set != 0) r_registers[being_set] <= setting_to;
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if (being_set != 0) r_registers[being_set] = setting_to;
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endtask
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uart_tx #(
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.CLK_FRE(FREQ),
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.BAUD_RATE(1000000)
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) tx (
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.clk(i_clk),
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.rst_n(1'b1),
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.tx_data(r_tx_data),
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.tx_data_valid(w_tx_send),
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.tx_data_ready(w_tx_ready),
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.tx_pin(o_uart_tx)
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// uart_tx #(
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// .CLK_FRE(FREQ / 1_000_000),
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// .BAUD_RATE(UART_BAUD)
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// ) tx (
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// .clk(i_clk),
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// .rst_n(1),
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// .tx_data(r_tx_data),
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// .tx_data_valid(w_tx_send),
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// .tx_data_ready(w_tx_ready),
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// .tx_pin(o_uart_tx)
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// );
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Multi7 display (
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.i_clk(i_clk),
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.i_hex({r_registers[1][7:0], r_registers[2][7:0]}),
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.o_segments_drive(o_segments_drive),
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.o_displays_neg(o_displays_neg)
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);
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// TODO: Bus
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@ -11,3 +11,25 @@ IO_LOC "o_uart_tx" 69;
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IO_PORT "o_uart_tx" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "i_clk" 4;
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IO_PORT "i_clk" PULL_MODE=UP BANK_VCCIO=1.8;
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IO_LOC "o_displays_neg[3]" 80;
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IO_PORT "o_displays_neg[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_displays_neg[2]" 76;
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IO_PORT "o_displays_neg[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_displays_neg[1]" 73;
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IO_PORT "o_displays_neg[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_displays_neg[0]" 74;
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IO_PORT "o_displays_neg[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_segments_drive[6]" 20;
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IO_PORT "o_segments_drive[6]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_segments_drive[5]" 19;
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IO_PORT "o_segments_drive[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_segments_drive[4]" 86;
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IO_PORT "o_segments_drive[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_segments_drive[3]" 53;
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IO_PORT "o_segments_drive[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_segments_drive[2]" 71;
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IO_PORT "o_segments_drive[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_segments_drive[1]" 18;
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IO_PORT "o_segments_drive[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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IO_LOC "o_segments_drive[0]" 72;
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IO_PORT "o_segments_drive[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
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@ -5,6 +5,8 @@
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`define UN_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
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`define TX 'h01
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`define TX_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
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`define NOP 'h02
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`define NOP_ARGS {ARG_N, ARG_N, ARG_N, ARG_N}
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// Binary register-register operations
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`define ADD8 'h03
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@ -19,6 +21,7 @@
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// Binary register-immediate operations
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`define ADDI8 'h2D
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`define ADDI8_ARGS {ARG_R, ARG_R, ARG_B, ARG_N}
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// Register-immediate bitshifts
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`define SLUI8 'h38
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259
src/memory.mi
259
src/memory.mi
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@ -1,259 +0,0 @@
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#File_format=Bin
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#Address_depth=256
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#Data_width=8
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00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
112
src/multi7.v
Normal file
112
src/multi7.v
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
// displays multiple BCD digits on multiplexed seven segment displays
|
||||
module Multi7 #(
|
||||
parameter DISPLAYS = 4,
|
||||
parameter FREQ = 27_000_000,
|
||||
parameter DELAY_US = 5000,
|
||||
parameter integer DELAY = FREQ * (DELAY_US / 1_000_000.0),
|
||||
parameter ENABLE_HEX = 1,
|
||||
parameter ENABLE_CUSTOM = 0
|
||||
) (
|
||||
i_clk,
|
||||
i_hex,
|
||||
i_custom,
|
||||
i_mode, // if hex and custom are both enabled, 0 selects hex mode and 1 selects custom
|
||||
o_segments_drive,
|
||||
o_displays_neg
|
||||
);
|
||||
|
||||
localparam d_0 = 7'b1111110;
|
||||
localparam d_1 = 7'b0110000;
|
||||
localparam d_2 = 7'b1101101;
|
||||
localparam d_3 = 7'b1111001;
|
||||
localparam d_4 = 7'b0110011;
|
||||
localparam d_5 = 7'b1011011;
|
||||
localparam d_6 = 7'b1011111;
|
||||
localparam d_7 = 7'b1110000;
|
||||
localparam d_8 = 7'b1111111;
|
||||
localparam d_9 = 7'b1111011;
|
||||
localparam d_a = 7'b1110111;
|
||||
localparam d_b = 7'b0011111;
|
||||
localparam d_c = 7'b1001110;
|
||||
localparam d_d = 7'b0111101;
|
||||
localparam d_e = 7'b1001111;
|
||||
localparam d_f = 7'b1000111;
|
||||
|
||||
input i_clk, i_mode;
|
||||
input [(ENABLE_HEX * (DISPLAYS*4-1)):0] i_hex;
|
||||
input [(ENABLE_CUSTOM * (DISPLAYS*7-1)):0] i_custom;
|
||||
|
||||
// 6543210
|
||||
// gfedcba
|
||||
output [6:0] o_segments_drive;
|
||||
output [(DISPLAYS-1):0] o_displays_neg;
|
||||
|
||||
reg [$clog2(DELAY):0] r_tick = 0;
|
||||
reg [(DISPLAYS*7-1):0] r_hex_state;
|
||||
reg [$clog2(DISPLAYS):0] r_display_select = 0;
|
||||
reg [(DISPLAYS-1):0] r_displays_neg = ~1;
|
||||
reg [6:0] r_display_output;
|
||||
|
||||
assign o_segments_drive = r_display_output;
|
||||
assign o_displays_neg = r_displays_neg;
|
||||
|
||||
always @(posedge i_clk) begin
|
||||
if (r_tick == DELAY - 1) begin
|
||||
r_tick <= 0;
|
||||
r_displays_neg <= (r_displays_neg << 1) | r_displays_neg[DISPLAYS-1];
|
||||
|
||||
if (r_display_select == DISPLAYS - 1) begin
|
||||
r_display_select <= 0;
|
||||
end else begin
|
||||
r_display_select <= r_display_select + 1;
|
||||
end
|
||||
end else begin
|
||||
r_tick <= r_tick + 1;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (ENABLE_HEX) begin
|
||||
for (genvar i = 0; i < DISPLAYS; i = i + 1) begin
|
||||
localparam TOP = i * 4 + 4 - 1;
|
||||
localparam BOTTOM = i * 4;
|
||||
localparam G = i * 7 + 7 - 1;
|
||||
localparam A = i * 7;
|
||||
|
||||
always @(i_hex[(TOP):(BOTTOM)]) begin
|
||||
case (i_hex[(TOP):(BOTTOM)])
|
||||
4'h0: r_hex_state[G:A] <= d_0;
|
||||
4'h1: r_hex_state[G:A] <= d_1;
|
||||
4'h2: r_hex_state[G:A] <= d_2;
|
||||
4'h3: r_hex_state[G:A] <= d_3;
|
||||
4'h4: r_hex_state[G:A] <= d_4;
|
||||
4'h5: r_hex_state[G:A] <= d_5;
|
||||
4'h6: r_hex_state[G:A] <= d_6;
|
||||
4'h7: r_hex_state[G:A] <= d_7;
|
||||
4'h8: r_hex_state[G:A] <= d_8;
|
||||
4'h9: r_hex_state[G:A] <= d_9;
|
||||
4'hA: r_hex_state[G:A] <= d_a;
|
||||
4'hB: r_hex_state[G:A] <= d_b;
|
||||
4'hC: r_hex_state[G:A] <= d_c;
|
||||
4'hD: r_hex_state[G:A] <= d_d;
|
||||
4'hE: r_hex_state[G:A] <= d_e;
|
||||
4'hF: r_hex_state[G:A] <= d_f;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (ENABLE_HEX && ENABLE_CUSTOM) begin
|
||||
always @(r_hex_state or i_custom or i_mode or r_display_select)
|
||||
r_display_output <= (i_mode ? i_custom : r_hex_state) >> (r_display_select * 7);
|
||||
end else if (ENABLE_HEX) begin
|
||||
always @(r_hex_state or r_display_select)
|
||||
r_display_output <= r_hex_state >> (r_display_select * 7);
|
||||
end else if (ENABLE_CUSTOM) begin
|
||||
always @(i_custom or r_display_select)
|
||||
r_display_output <= i_custom >> (r_display_select * 7);
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
35
src/programs/addi8.mi
Normal file
35
src/programs/addi8.mi
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
#File_format=Bin
|
||||
#Address_depth=32
|
||||
#Data_width=8
|
||||
00000000
|
||||
01001000
|
||||
00000001
|
||||
00100011
|
||||
00101101
|
||||
00000001
|
||||
00000001
|
||||
10000111
|
||||
00000001
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
|
|
@ -8,7 +8,8 @@ module tb_beepo(
|
|||
reg clk = 0;
|
||||
|
||||
Beepo #(
|
||||
.FREQ(1)
|
||||
.FREQ(1),
|
||||
.UART_BAUD(1_000_000)
|
||||
) bep (
|
||||
.i_clk(clk),
|
||||
.o_uart_tx(o_uart_tx)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
../src/instructions.v
|
||||
beepo.v
|
||||
../src/uart_tx.v
|
||||
../src/multi7.v
|
||||
spmem.v
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ module spMem(
|
|||
8'h48, 8'h02, 8'h46,
|
||||
8'h03, 8'h01, 8'h01, 8'h02,
|
||||
8'h01,
|
||||
168'h0
|
||||
160'h0
|
||||
};
|
||||
|
||||
reg [7:0] r_out;
|
||||
|
|
|
|||
Loading…
Reference in a new issue