Compare commits
2 commits
ce32cfd5fb
...
2bebf3a9ed
| Author | SHA1 | Date | |
|---|---|---|---|
 Bee
|
2bebf3a9ed | ||
|
Bee
|
2a2da899c7 |
1
.gitignore
vendored
1
.gitignore
vendored
|
|
@ -2,3 +2,4 @@ impl/
|
||||||
**/*.gprj
|
**/*.gprj
|
||||||
tests/*.vcd
|
tests/*.vcd
|
||||||
tests/out
|
tests/out
|
||||||
|
src/gowin_*/
|
||||||
|
|
@ -3,7 +3,7 @@
|
||||||
<UserConfig>
|
<UserConfig>
|
||||||
<Version>1.0</Version>
|
<Version>1.0</Version>
|
||||||
<FlowState>
|
<FlowState>
|
||||||
<Process ID="Synthesis" State="2"/>
|
<Process ID="Synthesis" State="4"/>
|
||||||
<Process ID="Pnr" State="4"/>
|
<Process ID="Pnr" State="4"/>
|
||||||
<Process ID="Gao" State="4"/>
|
<Process ID="Gao" State="4"/>
|
||||||
<Process ID="Rtl_Gao" State="2"/>
|
<Process ID="Rtl_Gao" State="2"/>
|
||||||
|
|
@ -20,5 +20,5 @@
|
||||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/holeybeepo_syn.rpt.html"/>
|
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/holeybeepo_syn.rpt.html"/>
|
||||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/holeybeepo_syn_rsc.xml"/>
|
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/holeybeepo_syn_rsc.xml"/>
|
||||||
</ResultFileList>
|
</ResultFileList>
|
||||||
<Ui>000000ff00000001fd00000002000000000000010000000250fc0200000001fc00000038000002500000008a01000018fa000000000200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc0000000000000776000000a500fffffffa000000000100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a500fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000000006700000025000000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000</Ui>
|
<Ui>000000ff00000001fd00000002000000000000010000000250fc0200000001fc00000038000002500000000000fffffffaffffffff0200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff00000000000000000000000300000776000000f2fc0100000001fc00000000000007760000000000fffffffaffffffff0100000003fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000000006700000025000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||||
</UserConfig>
|
</UserConfig>
|
||||||
|
|
|
||||||
23
src/beepo.v
23
src/beepo.v
|
|
@ -30,6 +30,7 @@ module Beepo #(
|
||||||
localparam NUM_REGS = 4;
|
localparam NUM_REGS = 4;
|
||||||
|
|
||||||
reg [2:0] r_state = IDLE;
|
reg [2:0] r_state = IDLE;
|
||||||
|
reg [63:0] r_tick = 0;
|
||||||
|
|
||||||
// UART tx
|
// UART tx
|
||||||
reg [7:0] r_tx_data = 0;
|
reg [7:0] r_tx_data = 0;
|
||||||
|
|
@ -64,6 +65,8 @@ module Beepo #(
|
||||||
|
|
||||||
always @(r_registers[1]) r_tx_data <= r_registers[1];
|
always @(r_registers[1]) r_tx_data <= r_registers[1];
|
||||||
|
|
||||||
|
always @(posedge i_clk) r_tick <= r_tick + 1;
|
||||||
|
|
||||||
always @(posedge i_clk) begin
|
always @(posedge i_clk) begin
|
||||||
case (r_state)
|
case (r_state)
|
||||||
IDLE: begin
|
IDLE: begin
|
||||||
|
|
@ -107,13 +110,13 @@ module Beepo #(
|
||||||
else begin
|
else begin
|
||||||
case (r_arg_current_type)
|
case (r_arg_current_type)
|
||||||
ARG_R: r_arg_regs[r_arg_index] <= w_mem_fetch;
|
ARG_R: r_arg_regs[r_arg_index] <= w_mem_fetch;
|
||||||
ARG_O: r_arg_addr[r_arg_bit-1+:8] <= w_mem_fetch;
|
ARG_O: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
|
||||||
ARG_P: r_arg_addr[r_arg_bit-1+:8] <= w_mem_fetch;
|
ARG_P: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
|
||||||
ARG_B: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
|
ARG_B: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
|
||||||
ARG_H: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
|
ARG_H: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
|
||||||
ARG_W: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
|
ARG_W: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
|
||||||
ARG_D: r_arg_imm[r_arg_bit-1+:8] <= w_mem_fetch;
|
ARG_D: r_arg_imm[r_arg_bit+:8] <= w_mem_fetch;
|
||||||
ARG_A: r_arg_addr[r_arg_bit-1+:8] <= w_mem_fetch;
|
ARG_A: r_arg_addr[r_arg_bit+:8] <= w_mem_fetch;
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
r_pc_latch <= r_pc;
|
r_pc_latch <= r_pc;
|
||||||
|
|
@ -129,7 +132,7 @@ module Beepo #(
|
||||||
if (r_arg_current_type == ARG_N) r_state <= EXEC;
|
if (r_arg_current_type == ARG_N) r_state <= EXEC;
|
||||||
else begin
|
else begin
|
||||||
r_arg_bit <= 0;
|
r_arg_bit <= 0;
|
||||||
r_arg_bytes <= ARG_SIZES[r_arg_current_type+:4];
|
r_arg_bytes <= ARG_SIZES[r_arg_current_type*4+:4];
|
||||||
|
|
||||||
case (r_arg_current_type)
|
case (r_arg_current_type)
|
||||||
ARG_R: r_arg_regs[r_arg_index] <= 0;
|
ARG_R: r_arg_regs[r_arg_index] <= 0;
|
||||||
|
|
@ -147,11 +150,11 @@ module Beepo #(
|
||||||
end
|
end
|
||||||
EXEC: begin
|
EXEC: begin
|
||||||
case (r_instr)
|
case (r_instr)
|
||||||
`ADD8: set_register(r_arg_regs[0], r_arg_regs[1] + r_arg_regs[2][7:0]);
|
`ADD8: set_register(r_arg_regs[0], r_registers[r_arg_regs[1]] + r_registers[r_arg_regs[2]][7:0]);
|
||||||
`LI8: set_register(r_arg_regs[0], r_arg_imm);
|
`LI8: set_register(r_arg_regs[0], r_arg_imm);
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
r_state <= IDLE;
|
r_state <= FETCHI;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
|
||||||
65280
src/first.mi
65280
src/first.mi
File diff suppressed because it is too large
Load diff
|
|
@ -1,17 +0,0 @@
|
||||||
[General]
|
|
||||||
ipc_version=4
|
|
||||||
file=gowin_sp
|
|
||||||
module=spMem
|
|
||||||
target_device=gw2ar18c-000
|
|
||||||
type=ram_sp
|
|
||||||
version=3.0
|
|
||||||
|
|
||||||
[Config]
|
|
||||||
BYTE_SIZE=0
|
|
||||||
DEPTH=65536
|
|
||||||
LANG=0
|
|
||||||
READ=0
|
|
||||||
RESET_MODE=true
|
|
||||||
WIDTH=8
|
|
||||||
WRITE=0
|
|
||||||
MEM_FILE=../first.mi
|
|
||||||
|
|
@ -1,18 +0,0 @@
|
||||||
-series GW2AR
|
|
||||||
-device GW2AR-18
|
|
||||||
-device_version C
|
|
||||||
-package QFN88
|
|
||||||
-part_number GW2AR-LV18QN88C8/I7
|
|
||||||
|
|
||||||
|
|
||||||
-mod_name spMem
|
|
||||||
-file_name gowin_sp
|
|
||||||
-path /home/bee/Projects/holeybeepo/src/gowin_sp/
|
|
||||||
-type RAM_SP
|
|
||||||
-file_type vlg
|
|
||||||
-depth 65536
|
|
||||||
-width 8
|
|
||||||
-read_mode bypass
|
|
||||||
-write_mode normal
|
|
||||||
-reset_mode sync
|
|
||||||
-init_file /home/bee/Projects/holeybeepo/src/first.mi
|
|
||||||
|
|
@ -1,849 +0,0 @@
|
||||||
//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
|
|
||||||
//All rights reserved.
|
|
||||||
//File Title: IP file
|
|
||||||
//GOWIN Version: V1.9.9 Beta-4 Education
|
|
||||||
//Part Number: GW2AR-LV18QN88C8/I7
|
|
||||||
//Device: GW2AR-18
|
|
||||||
//Device Version: C
|
|
||||||
//Created Time: Wed Nov 15 04:42:39 2023
|
|
||||||
|
|
||||||
module spMem (dout, clk, oce, ce, reset, wre, ad, din);
|
|
||||||
|
|
||||||
output [7:0] dout;
|
|
||||||
input clk;
|
|
||||||
input oce;
|
|
||||||
input ce;
|
|
||||||
input reset;
|
|
||||||
input wre;
|
|
||||||
input [15:0] ad;
|
|
||||||
input [7:0] din;
|
|
||||||
|
|
||||||
wire [30:0] sp_inst_0_dout_w;
|
|
||||||
wire [0:0] sp_inst_0_dout;
|
|
||||||
wire [30:0] sp_inst_1_dout_w;
|
|
||||||
wire [0:0] sp_inst_1_dout;
|
|
||||||
wire [30:0] sp_inst_2_dout_w;
|
|
||||||
wire [0:0] sp_inst_2_dout;
|
|
||||||
wire [30:0] sp_inst_3_dout_w;
|
|
||||||
wire [0:0] sp_inst_3_dout;
|
|
||||||
wire [30:0] sp_inst_4_dout_w;
|
|
||||||
wire [1:1] sp_inst_4_dout;
|
|
||||||
wire [30:0] sp_inst_5_dout_w;
|
|
||||||
wire [1:1] sp_inst_5_dout;
|
|
||||||
wire [30:0] sp_inst_6_dout_w;
|
|
||||||
wire [1:1] sp_inst_6_dout;
|
|
||||||
wire [30:0] sp_inst_7_dout_w;
|
|
||||||
wire [1:1] sp_inst_7_dout;
|
|
||||||
wire [30:0] sp_inst_8_dout_w;
|
|
||||||
wire [2:2] sp_inst_8_dout;
|
|
||||||
wire [30:0] sp_inst_9_dout_w;
|
|
||||||
wire [2:2] sp_inst_9_dout;
|
|
||||||
wire [30:0] sp_inst_10_dout_w;
|
|
||||||
wire [2:2] sp_inst_10_dout;
|
|
||||||
wire [30:0] sp_inst_11_dout_w;
|
|
||||||
wire [2:2] sp_inst_11_dout;
|
|
||||||
wire [30:0] sp_inst_12_dout_w;
|
|
||||||
wire [3:3] sp_inst_12_dout;
|
|
||||||
wire [30:0] sp_inst_13_dout_w;
|
|
||||||
wire [3:3] sp_inst_13_dout;
|
|
||||||
wire [30:0] sp_inst_14_dout_w;
|
|
||||||
wire [3:3] sp_inst_14_dout;
|
|
||||||
wire [30:0] sp_inst_15_dout_w;
|
|
||||||
wire [3:3] sp_inst_15_dout;
|
|
||||||
wire [30:0] sp_inst_16_dout_w;
|
|
||||||
wire [4:4] sp_inst_16_dout;
|
|
||||||
wire [30:0] sp_inst_17_dout_w;
|
|
||||||
wire [4:4] sp_inst_17_dout;
|
|
||||||
wire [30:0] sp_inst_18_dout_w;
|
|
||||||
wire [4:4] sp_inst_18_dout;
|
|
||||||
wire [30:0] sp_inst_19_dout_w;
|
|
||||||
wire [4:4] sp_inst_19_dout;
|
|
||||||
wire [30:0] sp_inst_20_dout_w;
|
|
||||||
wire [5:5] sp_inst_20_dout;
|
|
||||||
wire [30:0] sp_inst_21_dout_w;
|
|
||||||
wire [5:5] sp_inst_21_dout;
|
|
||||||
wire [30:0] sp_inst_22_dout_w;
|
|
||||||
wire [5:5] sp_inst_22_dout;
|
|
||||||
wire [30:0] sp_inst_23_dout_w;
|
|
||||||
wire [5:5] sp_inst_23_dout;
|
|
||||||
wire [30:0] sp_inst_24_dout_w;
|
|
||||||
wire [6:6] sp_inst_24_dout;
|
|
||||||
wire [30:0] sp_inst_25_dout_w;
|
|
||||||
wire [6:6] sp_inst_25_dout;
|
|
||||||
wire [30:0] sp_inst_26_dout_w;
|
|
||||||
wire [6:6] sp_inst_26_dout;
|
|
||||||
wire [30:0] sp_inst_27_dout_w;
|
|
||||||
wire [6:6] sp_inst_27_dout;
|
|
||||||
wire [30:0] sp_inst_28_dout_w;
|
|
||||||
wire [7:7] sp_inst_28_dout;
|
|
||||||
wire [30:0] sp_inst_29_dout_w;
|
|
||||||
wire [7:7] sp_inst_29_dout;
|
|
||||||
wire [30:0] sp_inst_30_dout_w;
|
|
||||||
wire [7:7] sp_inst_30_dout;
|
|
||||||
wire [30:0] sp_inst_31_dout_w;
|
|
||||||
wire [7:7] sp_inst_31_dout;
|
|
||||||
wire dff_q_0;
|
|
||||||
wire dff_q_1;
|
|
||||||
wire mux_o_0;
|
|
||||||
wire mux_o_1;
|
|
||||||
wire mux_o_3;
|
|
||||||
wire mux_o_4;
|
|
||||||
wire mux_o_6;
|
|
||||||
wire mux_o_7;
|
|
||||||
wire mux_o_9;
|
|
||||||
wire mux_o_10;
|
|
||||||
wire mux_o_12;
|
|
||||||
wire mux_o_13;
|
|
||||||
wire mux_o_15;
|
|
||||||
wire mux_o_16;
|
|
||||||
wire mux_o_18;
|
|
||||||
wire mux_o_19;
|
|
||||||
wire mux_o_21;
|
|
||||||
wire mux_o_22;
|
|
||||||
wire ce_w;
|
|
||||||
wire gw_gnd;
|
|
||||||
|
|
||||||
assign ce_w = ~wre & ce;
|
|
||||||
assign gw_gnd = 1'b0;
|
|
||||||
|
|
||||||
SP sp_inst_0 (
|
|
||||||
.DO({sp_inst_0_dout_w[30:0],sp_inst_0_dout[0]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_0.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_0.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_0.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_0.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_0.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_0.INIT_RAM_00 = 256'h000000000000000000000000000000000000000000000000000000000000038C;
|
|
||||||
|
|
||||||
SP sp_inst_1 (
|
|
||||||
.DO({sp_inst_1_dout_w[30:0],sp_inst_1_dout[0]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_1.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_1.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_1.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_1.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_1.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_2 (
|
|
||||||
.DO({sp_inst_2_dout_w[30:0],sp_inst_2_dout[0]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_2.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_2.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_2.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_2.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_2.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_3 (
|
|
||||||
.DO({sp_inst_3_dout_w[30:0],sp_inst_3_dout[0]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[0]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_3.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_3.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_3.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_3.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_3.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_4 (
|
|
||||||
.DO({sp_inst_4_dout_w[30:0],sp_inst_4_dout[1]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_4.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_4.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_4.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_4.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_4.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_4.INIT_RAM_00 = 256'h00000000000000000000000000000000000000000000000000000000000004E8;
|
|
||||||
|
|
||||||
SP sp_inst_5 (
|
|
||||||
.DO({sp_inst_5_dout_w[30:0],sp_inst_5_dout[1]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_5.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_5.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_5.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_5.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_5.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_6 (
|
|
||||||
.DO({sp_inst_6_dout_w[30:0],sp_inst_6_dout[1]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_6.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_6.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_6.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_6.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_6.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_7 (
|
|
||||||
.DO({sp_inst_7_dout_w[30:0],sp_inst_7_dout[1]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[1]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_7.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_7.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_7.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_7.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_7.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_8 (
|
|
||||||
.DO({sp_inst_8_dout_w[30:0],sp_inst_8_dout[2]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_8.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_8.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_8.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_8.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_8.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_8.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000040;
|
|
||||||
|
|
||||||
SP sp_inst_9 (
|
|
||||||
.DO({sp_inst_9_dout_w[30:0],sp_inst_9_dout[2]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_9.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_9.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_9.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_9.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_9.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_10 (
|
|
||||||
.DO({sp_inst_10_dout_w[30:0],sp_inst_10_dout[2]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_10.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_10.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_10.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_10.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_10.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_11 (
|
|
||||||
.DO({sp_inst_11_dout_w[30:0],sp_inst_11_dout[2]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[2]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_11.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_11.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_11.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_11.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_11.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_12 (
|
|
||||||
.DO({sp_inst_12_dout_w[30:0],sp_inst_12_dout[3]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_12.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_12.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_12.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_12.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_12.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_12.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000012;
|
|
||||||
|
|
||||||
SP sp_inst_13 (
|
|
||||||
.DO({sp_inst_13_dout_w[30:0],sp_inst_13_dout[3]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_13.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_13.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_13.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_13.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_13.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_14 (
|
|
||||||
.DO({sp_inst_14_dout_w[30:0],sp_inst_14_dout[3]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_14.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_14.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_14.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_14.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_14.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_15 (
|
|
||||||
.DO({sp_inst_15_dout_w[30:0],sp_inst_15_dout[3]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[3]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_15.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_15.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_15.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_15.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_15.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_16 (
|
|
||||||
.DO({sp_inst_16_dout_w[30:0],sp_inst_16_dout[4]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_16.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_16.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_16.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_16.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_16.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_16.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
|
|
||||||
SP sp_inst_17 (
|
|
||||||
.DO({sp_inst_17_dout_w[30:0],sp_inst_17_dout[4]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_17.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_17.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_17.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_17.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_17.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_18 (
|
|
||||||
.DO({sp_inst_18_dout_w[30:0],sp_inst_18_dout[4]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_18.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_18.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_18.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_18.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_18.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_19 (
|
|
||||||
.DO({sp_inst_19_dout_w[30:0],sp_inst_19_dout[4]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[4]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_19.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_19.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_19.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_19.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_19.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_20 (
|
|
||||||
.DO({sp_inst_20_dout_w[30:0],sp_inst_20_dout[5]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_20.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_20.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_20.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_20.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_20.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_20.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000008;
|
|
||||||
|
|
||||||
SP sp_inst_21 (
|
|
||||||
.DO({sp_inst_21_dout_w[30:0],sp_inst_21_dout[5]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_21.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_21.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_21.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_21.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_21.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_22 (
|
|
||||||
.DO({sp_inst_22_dout_w[30:0],sp_inst_22_dout[5]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_22.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_22.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_22.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_22.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_22.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_23 (
|
|
||||||
.DO({sp_inst_23_dout_w[30:0],sp_inst_23_dout[5]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[5]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_23.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_23.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_23.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_23.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_23.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_24 (
|
|
||||||
.DO({sp_inst_24_dout_w[30:0],sp_inst_24_dout[6]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_24.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_24.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_24.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_24.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_24.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_24.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000052;
|
|
||||||
|
|
||||||
SP sp_inst_25 (
|
|
||||||
.DO({sp_inst_25_dout_w[30:0],sp_inst_25_dout[6]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_25.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_25.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_25.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_25.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_25.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_26 (
|
|
||||||
.DO({sp_inst_26_dout_w[30:0],sp_inst_26_dout[6]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_26.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_26.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_26.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_26.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_26.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_27 (
|
|
||||||
.DO({sp_inst_27_dout_w[30:0],sp_inst_27_dout[6]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[6]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_27.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_27.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_27.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_27.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_27.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_28 (
|
|
||||||
.DO({sp_inst_28_dout_w[30:0],sp_inst_28_dout[7]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_28.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_28.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_28.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_28.BLK_SEL = 3'b000;
|
|
||||||
defparam sp_inst_28.RESET_MODE = "SYNC";
|
|
||||||
defparam sp_inst_28.INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
|
|
||||||
SP sp_inst_29 (
|
|
||||||
.DO({sp_inst_29_dout_w[30:0],sp_inst_29_dout[7]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_29.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_29.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_29.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_29.BLK_SEL = 3'b001;
|
|
||||||
defparam sp_inst_29.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_30 (
|
|
||||||
.DO({sp_inst_30_dout_w[30:0],sp_inst_30_dout[7]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_30.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_30.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_30.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_30.BLK_SEL = 3'b010;
|
|
||||||
defparam sp_inst_30.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
SP sp_inst_31 (
|
|
||||||
.DO({sp_inst_31_dout_w[30:0],sp_inst_31_dout[7]}),
|
|
||||||
.CLK(clk),
|
|
||||||
.OCE(oce),
|
|
||||||
.CE(ce),
|
|
||||||
.RESET(reset),
|
|
||||||
.WRE(wre),
|
|
||||||
.BLKSEL({gw_gnd,ad[15],ad[14]}),
|
|
||||||
.AD(ad[13:0]),
|
|
||||||
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7]})
|
|
||||||
);
|
|
||||||
|
|
||||||
defparam sp_inst_31.READ_MODE = 1'b0;
|
|
||||||
defparam sp_inst_31.WRITE_MODE = 2'b00;
|
|
||||||
defparam sp_inst_31.BIT_WIDTH = 1;
|
|
||||||
defparam sp_inst_31.BLK_SEL = 3'b011;
|
|
||||||
defparam sp_inst_31.RESET_MODE = "SYNC";
|
|
||||||
|
|
||||||
DFFE dff_inst_0 (
|
|
||||||
.Q(dff_q_0),
|
|
||||||
.D(ad[15]),
|
|
||||||
.CLK(clk),
|
|
||||||
.CE(ce_w)
|
|
||||||
);
|
|
||||||
DFFE dff_inst_1 (
|
|
||||||
.Q(dff_q_1),
|
|
||||||
.D(ad[14]),
|
|
||||||
.CLK(clk),
|
|
||||||
.CE(ce_w)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_0 (
|
|
||||||
.O(mux_o_0),
|
|
||||||
.I0(sp_inst_0_dout[0]),
|
|
||||||
.I1(sp_inst_1_dout[0]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_1 (
|
|
||||||
.O(mux_o_1),
|
|
||||||
.I0(sp_inst_2_dout[0]),
|
|
||||||
.I1(sp_inst_3_dout[0]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_2 (
|
|
||||||
.O(dout[0]),
|
|
||||||
.I0(mux_o_0),
|
|
||||||
.I1(mux_o_1),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_3 (
|
|
||||||
.O(mux_o_3),
|
|
||||||
.I0(sp_inst_4_dout[1]),
|
|
||||||
.I1(sp_inst_5_dout[1]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_4 (
|
|
||||||
.O(mux_o_4),
|
|
||||||
.I0(sp_inst_6_dout[1]),
|
|
||||||
.I1(sp_inst_7_dout[1]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_5 (
|
|
||||||
.O(dout[1]),
|
|
||||||
.I0(mux_o_3),
|
|
||||||
.I1(mux_o_4),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_6 (
|
|
||||||
.O(mux_o_6),
|
|
||||||
.I0(sp_inst_8_dout[2]),
|
|
||||||
.I1(sp_inst_9_dout[2]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_7 (
|
|
||||||
.O(mux_o_7),
|
|
||||||
.I0(sp_inst_10_dout[2]),
|
|
||||||
.I1(sp_inst_11_dout[2]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_8 (
|
|
||||||
.O(dout[2]),
|
|
||||||
.I0(mux_o_6),
|
|
||||||
.I1(mux_o_7),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_9 (
|
|
||||||
.O(mux_o_9),
|
|
||||||
.I0(sp_inst_12_dout[3]),
|
|
||||||
.I1(sp_inst_13_dout[3]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_10 (
|
|
||||||
.O(mux_o_10),
|
|
||||||
.I0(sp_inst_14_dout[3]),
|
|
||||||
.I1(sp_inst_15_dout[3]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_11 (
|
|
||||||
.O(dout[3]),
|
|
||||||
.I0(mux_o_9),
|
|
||||||
.I1(mux_o_10),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_12 (
|
|
||||||
.O(mux_o_12),
|
|
||||||
.I0(sp_inst_16_dout[4]),
|
|
||||||
.I1(sp_inst_17_dout[4]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_13 (
|
|
||||||
.O(mux_o_13),
|
|
||||||
.I0(sp_inst_18_dout[4]),
|
|
||||||
.I1(sp_inst_19_dout[4]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_14 (
|
|
||||||
.O(dout[4]),
|
|
||||||
.I0(mux_o_12),
|
|
||||||
.I1(mux_o_13),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_15 (
|
|
||||||
.O(mux_o_15),
|
|
||||||
.I0(sp_inst_20_dout[5]),
|
|
||||||
.I1(sp_inst_21_dout[5]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_16 (
|
|
||||||
.O(mux_o_16),
|
|
||||||
.I0(sp_inst_22_dout[5]),
|
|
||||||
.I1(sp_inst_23_dout[5]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_17 (
|
|
||||||
.O(dout[5]),
|
|
||||||
.I0(mux_o_15),
|
|
||||||
.I1(mux_o_16),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_18 (
|
|
||||||
.O(mux_o_18),
|
|
||||||
.I0(sp_inst_24_dout[6]),
|
|
||||||
.I1(sp_inst_25_dout[6]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_19 (
|
|
||||||
.O(mux_o_19),
|
|
||||||
.I0(sp_inst_26_dout[6]),
|
|
||||||
.I1(sp_inst_27_dout[6]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_20 (
|
|
||||||
.O(dout[6]),
|
|
||||||
.I0(mux_o_18),
|
|
||||||
.I1(mux_o_19),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_21 (
|
|
||||||
.O(mux_o_21),
|
|
||||||
.I0(sp_inst_28_dout[7]),
|
|
||||||
.I1(sp_inst_29_dout[7]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_22 (
|
|
||||||
.O(mux_o_22),
|
|
||||||
.I0(sp_inst_30_dout[7]),
|
|
||||||
.I1(sp_inst_31_dout[7]),
|
|
||||||
.S0(dff_q_1)
|
|
||||||
);
|
|
||||||
MUX2 mux_inst_23 (
|
|
||||||
.O(dout[7]),
|
|
||||||
.I0(mux_o_21),
|
|
||||||
.I1(mux_o_22),
|
|
||||||
.S0(dff_q_0)
|
|
||||||
);
|
|
||||||
endmodule //spMem
|
|
||||||
|
|
@ -1,24 +0,0 @@
|
||||||
//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
|
|
||||||
//All rights reserved.
|
|
||||||
//File Title: Template file for instantiation
|
|
||||||
//GOWIN Version: V1.9.9 Beta-4 Education
|
|
||||||
//Part Number: GW2AR-LV18QN88C8/I7
|
|
||||||
//Device: GW2AR-18
|
|
||||||
//Device Version: C
|
|
||||||
//Created Time: Wed Nov 15 04:42:39 2023
|
|
||||||
|
|
||||||
//Change the instance name and port connections to the signal names
|
|
||||||
//--------Copy here to design--------
|
|
||||||
|
|
||||||
spMem your_instance_name(
|
|
||||||
.dout(dout_o), //output [7:0] dout
|
|
||||||
.clk(clk_i), //input clk
|
|
||||||
.oce(oce_i), //input oce
|
|
||||||
.ce(ce_i), //input ce
|
|
||||||
.reset(reset_i), //input reset
|
|
||||||
.wre(wre_i), //input wre
|
|
||||||
.ad(ad_i), //input [15:0] ad
|
|
||||||
.din(din_i) //input [7:0] din
|
|
||||||
);
|
|
||||||
|
|
||||||
//--------Copy end-------------------
|
|
||||||
|
|
@ -19,7 +19,8 @@ always #(CLK_PERIOD/2) clk=~clk;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
$dumpfile("dump.vcd");
|
$dumpfile("dump.vcd");
|
||||||
$dumpvars(0, tb_beepo, bep.r_registers[1],
|
$dumpvars(0, tb_beepo,
|
||||||
|
bep.r_registers[1], bep.r_registers[2],
|
||||||
bep.r_arg_types[0], bep.r_arg_types[1],
|
bep.r_arg_types[0], bep.r_arg_types[1],
|
||||||
bep.r_arg_types[2], bep.r_arg_types[3],
|
bep.r_arg_types[2], bep.r_arg_types[3],
|
||||||
bep.r_arg_regs[0], bep.r_arg_regs[1],
|
bep.r_arg_regs[0], bep.r_arg_regs[1],
|
||||||
|
|
|
||||||
|
|
@ -16,5 +16,11 @@ module spMem(
|
||||||
168'h0
|
168'h0
|
||||||
};
|
};
|
||||||
|
|
||||||
assign dout = mem[ad*8+:8];
|
reg [7:0] r_out;
|
||||||
|
|
||||||
|
assign dout = r_out;
|
||||||
|
|
||||||
|
always @(negedge clk) begin
|
||||||
|
r_out <= mem[ad*8+:8];
|
||||||
|
end
|
||||||
endmodule
|
endmodule
|
||||||
Loading…
Reference in a new issue