`include "../src/beepo.v"
`timescale 100us/10ns

`define assert(signal, value) \
    if (signal !== value) begin \
        $display("ASSERTION FAILED in %m: signal != value"); \
        $finish; \
    end

module tb_beepo();
    localparam T_STLD = 0;
    localparam T_STLD_HALF = 1;
    localparam T_STLD_DOUBLE = 2;

    localparam T_TESTS = 3;

    reg r_clk = 0;
    reg r_resume = 0;
    reg [1:0] r_test = 0;

    wire w_breakpoint;

    Beepo #(
        .FREQ(1)
    ) bep (
        .i_clk(r_clk),
        .i_resume(r_resume),
        .o_breakpoint(w_breakpoint)
    );

    localparam CLK_PERIOD = 1.0;
    always #(CLK_PERIOD/2) r_clk=~r_clk;

    initial begin
        $dumpfile("mem/build/dump.vcd");
        $dumpvars(0, tb_beepo,
            bep.r_arg_regs[0], bep.r_arg_regs[1],
            bep.r_arg_regs[2], bep.r_arg_regs[3],
            bep.r_registers[1], bep.r_registers[2],
            bep.r_registers[3], bep.r_registers[4]
        );
    end

    // should probably do more granular tests
    always @(posedge w_breakpoint) begin
        $display("BREAK");
        case (r_test)
            T_STLD: begin
                // `assert(bep.r_registers[1], 64'h1020304050607080);
                `assert(bep.r_registers[1], 16'h1020);
                $display("[MEM] ST/LD test passed");
            end
            T_STLD_HALF: begin
                // `assert(bep.r_registers[2], 64'h0000000010203040);
                `assert(bep.r_registers[2], 16'h10);
                $display("[MEM] ST/LD Half test passed");
            end
            T_STLD_DOUBLE: begin
                // `assert(bep.r_registers[3], 64'h1010202030304040);
                // `assert(bep.r_registers[4], 64'h5050606070708080);
                `assert(bep.r_registers[3], 64'h1010);
                `assert(bep.r_registers[4], 64'h5050);
                $display("[MEM] ST/LD Double test passed");
            end
        endcase

        r_test = r_test + 1;

        if (r_test == T_TESTS) begin
            $display("[MEM] All tests passed");
            $finish;
        end

        r_resume = 1;
        #2 r_resume = 0;
    end

    initial #100000 begin
        $display("[ADDING] Timeout");
        $finish;
    end
endmodule