`include "../../src/beepo.v"
`timescale 100us/10ns

`define assert(signal, value) \
    if (signal !== value) begin \
        $display("ASSERTION FAILED in %m: signal != value"); \
        $finish; \
    end

module tb_adding(
    output o_uart_tx
);

reg clk = 0;

Beepo #(
    .FREQ(1),
    .UART_BAUD(1_000_000)
) bep (
    .i_clk(clk),
    .o_uart_tx(o_uart_tx)
);
    localparam CLK_PERIOD = 1.0;
    always #(CLK_PERIOD/2) clk=~clk;

    initial begin
        $dumpfile("dump.vcd");
        $dumpvars(0, tb_adding,
            bep.r_registers[1], bep.r_registers[2],
            bep.r_arg_types[0], bep.r_arg_types[1],
            bep.r_arg_types[2], bep.r_arg_types[3],
            bep.r_arg_regs[0], bep.r_arg_regs[1],
            bep.r_arg_regs[2], bep.r_arg_regs[3]
        );
    end

    // should probably do more tests than just the end
    initial #10000 begin
        `assert(bep.r_registers[1], 64'h2020202040406090);
        $finish;
    end
endmodule