module spMem(
    output [7:0] dout,
    input clk,
    input oce,
    input ce,
    input reset,
    input wre,
    input [15:0] ad,
    input [7:0] din
);
    reg [0:543] mem = {
        8'h0,
        8'h48, 8'h01,  8'h10,               // r1 <- 0x10
        8'h49, 8'h02, 16'h1010,             // r2 <- 0x1010
        8'h4A, 8'h03, 32'h10101010,         // r3 <- 0x10101010
        8'h4B, 8'h04, 64'h1010101010101010, // r4 <- 0x1010101010101010
        8'h03, 8'h01,  8'h01,  8'h01,       // r1 <- r1 + r1    (r1 = 0x20)
        8'h04, 8'h01,  8'h01,  8'h02,       // r1 <- r1 + r2    (r1 = 0x1030)
        8'h05, 8'h01,  8'h01,  8'h03,       // r1 <- r1 + r3    (r1 = 0x10102040)
        8'h06, 8'h01,  8'h01,  8'h04,       // r1 <- r1 + r4    (r1 = 0x1010101020203050)
        8'h2D, 8'h01,  8'h01,  8'h10,       // r1 <- r1 + 0x10  (r1 = 0x1010101020203060)
        8'h2E, 8'h01,  8'h01, 16'h1010,     // r1 <- r1 + 0x1010    (r1 = 0x1010101020204070)
        8'h2F, 8'h01,  8'h01, 32'h10101010, // r1 <- r1 + 0x10101010    (r1 = 0x1010101030305080)
        8'h30, 8'h01,  8'h01, 64'h1010101010101010,  // r1 <- r1 + 0x1010101010101010    (r1 = 0x2020202040406090)
        8'h01                               // die
    };

    reg [7:0] r_out;

    assign dout = r_out;

    always @(negedge clk) begin
        r_out <= mem[ad*8+:8];
    end
endmodule