`include "../src/beepo.v"
`timescale 100us/10ns

module tb_beepo(
    output o_uart_tx
);

reg clk = 0;

Beepo #(
    .FREQ(1),
    .UART_BAUD(1_000_000)
) bep (
    .i_clk(clk),
    .o_uart_tx(o_uart_tx)
);

localparam CLK_PERIOD = 1.0;
always #(CLK_PERIOD/2) clk=~clk;

initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, tb_beepo,
        bep.r_registers[1], bep.r_registers[2],
        bep.r_arg_types[0], bep.r_arg_types[1],
        bep.r_arg_types[2], bep.r_arg_types[3],
        bep.r_arg_regs[0], bep.r_arg_regs[1],
        bep.r_arg_regs[2], bep.r_arg_regs[3]
    );
end

initial #10000 $finish;

endmodule