module spMem(
    output [7:0] dout,
    input clk,
    input oce,
    input ce,
    input reset,
    input wre,
    input [15:0] ad,
    input [7:0] din
);
    // gets replaced with the memory for the program to run
    reg [0:18446744073709551615] mem = 0'h;

    reg [15:0]  r_ad_prev = 0;
    reg [7:0]   r_out;

    assign dout = r_out;

    always @(negedge clk) begin
        // one full clock cycle before being fetched
        if (r_ad_prev == ad) r_out <= mem[ad*8+:8];
        else r_ad_prev = ad;
    end
endmodule