82 lines
2.2 KiB
Verilog
82 lines
2.2 KiB
Verilog
`include "../src/beepo.v"
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`timescale 100us/10ns
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`define assert(signal, value) \
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if (signal !== value) begin \
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$display("ASSERTION FAILED in %m: signal != value"); \
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$finish; \
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end
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module tb_beepo();
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localparam T_STLD = 0;
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localparam T_STLD_HALF = 1;
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localparam T_STLD_DOUBLE = 2;
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localparam T_TESTS = 3;
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reg r_clk = 0;
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reg r_resume = 0;
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reg [1:0] r_test = 0;
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wire w_breakpoint;
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Beepo #(
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.FREQ(1)
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) bep (
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.i_clk(r_clk),
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.i_resume(r_resume),
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.o_breakpoint(w_breakpoint)
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);
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localparam CLK_PERIOD = 1.0;
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always #(CLK_PERIOD/2) r_clk=~r_clk;
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initial begin
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$dumpfile("mem/build/dump.vcd");
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$dumpvars(0, tb_beepo,
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bep.r_arg_regs[0], bep.r_arg_regs[1],
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bep.r_arg_regs[2], bep.r_arg_regs[3],
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bep.r_registers[1], bep.r_registers[2],
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bep.r_registers[3], bep.r_registers[4]
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);
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end
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// should probably do more granular tests
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always @(posedge w_breakpoint) begin
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$display("BREAK");
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case (r_test)
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T_STLD: begin
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// `assert(bep.r_registers[1], 64'h1020304050607080);
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`assert(bep.r_registers[1], 16'h1020);
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$display("[MEM] ST/LD test passed");
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end
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T_STLD_HALF: begin
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// `assert(bep.r_registers[2], 64'h0000000010203040);
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`assert(bep.r_registers[2], 16'h10);
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$display("[MEM] ST/LD Half test passed");
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end
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T_STLD_DOUBLE: begin
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// `assert(bep.r_registers[3], 64'h1010202030304040);
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// `assert(bep.r_registers[4], 64'h5050606070708080);
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`assert(bep.r_registers[3], 64'h1010);
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`assert(bep.r_registers[4], 64'h5050);
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$display("[MEM] ST/LD Double test passed");
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end
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endcase
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r_test = r_test + 1;
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if (r_test == T_TESTS) begin
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$display("[MEM] All tests passed");
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$finish;
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end
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r_resume = 1;
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#2 r_resume = 0;
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end
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initial #100000 begin
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$display("[ADDING] Timeout");
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$finish;
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end
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endmodule |