28 lines
578 B
Verilog
28 lines
578 B
Verilog
module spMem(
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output [7:0] dout,
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input clk,
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input oce,
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input ce,
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input reset,
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input wre,
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input [15:0] ad,
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input [7:0] din
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);
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// gets replaced with the memory for the program to run
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$$insert_mem$$
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reg [15:0] r_ad_prev = 0;
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reg [7:0] r_out;
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assign dout = r_out;
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always @(negedge clk) begin
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// one full clock cycle before being fetched
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if (r_ad_prev == ad) begin
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if (wre == 1) mem[ad*8+:8] = din;
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r_out <= mem[ad*8+:8];
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end
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else r_ad_prev = ad;
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end
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endmodule |