35 lines
1.3 KiB
Verilog
35 lines
1.3 KiB
Verilog
module spMem(
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output [7:0] dout,
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input clk,
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input oce,
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input ce,
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input reset,
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input wre,
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input [15:0] ad,
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input [7:0] din
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);
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reg [0:543] mem = {
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8'h0,
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8'h48, 8'h01, 8'h10, // r1 <- 0x10
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8'h49, 8'h02, 16'h1010, // r2 <- 0x1010
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8'h4A, 8'h03, 32'h10101010, // r3 <- 0x10101010
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8'h4B, 8'h04, 64'h1010101010101010, // r4 <- 0x1010101010101010
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8'h03, 8'h01, 8'h01, 8'h01, // r1 <- r1 + r1 (r1 = 0x20)
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8'h04, 8'h01, 8'h01, 8'h02, // r1 <- r1 + r2 (r1 = 0x1030)
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8'h05, 8'h01, 8'h01, 8'h03, // r1 <- r1 + r3 (r1 = 0x10102040)
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8'h06, 8'h01, 8'h01, 8'h04, // r1 <- r1 + r4 (r1 = 0x1010101020203050)
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8'h2D, 8'h01, 8'h01, 8'h10, // r1 <- r1 + 0x10 (r1 = 0x1010101020203060)
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8'h2E, 8'h01, 8'h01, 16'h1010, // r1 <- r1 + 0x1010 (r1 = 0x1010101020204070)
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8'h2F, 8'h01, 8'h01, 32'h10101010, // r1 <- r1 + 0x10101010 (r1 = 0x1010101030305080)
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8'h30, 8'h01, 8'h01, 64'h1010101010101010, // r1 <- r1 + 0x1010101010101010 (r1 = 0x2020202040406090)
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8'h01 // die
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};
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reg [7:0] r_out;
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assign dout = r_out;
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always @(negedge clk) begin
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r_out <= mem[ad*8+:8];
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end
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endmodule |