32 lines
567 B
Verilog
32 lines
567 B
Verilog
`include "../src/beepo.v"
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`timescale 100us/10ns
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module tb_beepo(
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output o_uart_tx
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);
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reg clk = 0;
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Beepo #(
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.FREQ(1)
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) bep (
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.i_clk(clk),
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.o_uart_tx(o_uart_tx)
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);
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localparam CLK_PERIOD = 1.0;
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always #(CLK_PERIOD/2) clk=~clk;
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars(0, tb_beepo, bep.r_registers[1],
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bep.r_arg_types[0], bep.r_arg_types[1],
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bep.r_arg_types[2], bep.r_arg_types[3],
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bep.r_arg_regs[0], bep.r_arg_regs[1],
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bep.r_arg_regs[2], bep.r_arg_regs[3]
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);
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end
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initial #10000 $finish;
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endmodule |