forked from AbleOS/holey-bytes
Changed relative addressing
ondra05
parent
f0d162a2e3
commit
cb806b3881
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@ -1,15 +1,15 @@
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#![no_std]
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pub type OpR = u8;
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type OpR = u8;
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pub type OpA = u64;
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pub type OpO = u32;
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pub type OpP = u16;
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type OpA = u64;
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type OpO = u32;
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type OpP = u16;
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pub type OpB = u8;
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pub type OpH = u16;
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pub type OpW = u32;
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pub type OpD = u64;
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type OpB = u8;
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type OpH = u16;
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type OpW = u32;
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type OpD = u64;
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/// # Safety
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/// Has to be valid to be decoded from bytecode.
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@ -38,13 +38,12 @@ define_items! {
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OpsRRPH (OpR, OpR, OpP, OpH),
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OpsRRO (OpR, OpR, OpO ),
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OpsRRP (OpR, OpR, OpP ),
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OpsO (OpO, ),
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OpsP (OpP, ),
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OpsN ( ),
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}
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unsafe impl BytecodeItem for OpA {}
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unsafe impl BytecodeItem for OpB {}
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unsafe impl BytecodeItem for OpO {}
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unsafe impl BytecodeItem for OpP {}
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unsafe impl BytecodeItem for () {}
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unsafe impl BytecodeItem for u8 {}
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::with_builtin_macros::with_builtin! {
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let $spec = include_from_root!("instructions.in") in {
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@ -2,6 +2,8 @@
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//!
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//! Have fun
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use hbbytecode::OpsN;
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use {
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super::{
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bmc::BlockCopier,
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@ -9,14 +11,22 @@ use {
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value::{Value, ValueVariant},
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Vm, VmRunError, VmRunOk,
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},
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crate::mem::{addr::AddressOp, Address},
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core::{cmp::Ordering, mem::size_of, ops},
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crate::mem::Address,
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core::{cmp::Ordering, ops},
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hbbytecode::{
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BytecodeItem, OpA, OpO, OpP, OpsRD, OpsRR, OpsRRAH, OpsRRB, OpsRRD, OpsRRH, OpsRRO,
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OpsRROH, OpsRRP, OpsRRPH, OpsRRR, OpsRRRR, OpsRRW,
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BytecodeItem, OpsO, OpsP, OpsRD, OpsRR, OpsRRAH, OpsRRB, OpsRRD, OpsRRH, OpsRRO, OpsRROH,
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OpsRRP, OpsRRPH, OpsRRR, OpsRRRR, OpsRRW,
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},
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};
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macro_rules! handler {
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($self:expr, |$ty:ident ($($ident:pat),* $(,)?)| $expr:expr) => {{
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let $ty($($ident),*) = $self.decode::<$ty>();
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#[allow(clippy::no_effect)] $expr;
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$self.bump_pc::<$ty>();
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}};
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}
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impl<Mem, const TIMER_QUOTIENT: usize> Vm<Mem, TIMER_QUOTIENT>
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where
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Mem: Memory,
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@ -54,14 +64,14 @@ where
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.ok_or(VmRunError::ProgramFetchLoadEx(self.pc as _))?
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{
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UN => {
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self.decode::<()>();
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self.bump_pc::<OpsN>();
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return Err(VmRunError::Unreachable);
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}
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TX => {
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self.decode::<()>();
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self.bump_pc::<OpsN>();
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return Ok(VmRunOk::End);
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}
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NOP => self.decode::<()>(),
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NOP => handler!(self, |OpsN()| ()),
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ADD => self.binary_op(u64::wrapping_add),
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SUB => self.binary_op(u64::wrapping_sub),
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MUL => self.binary_op(u64::wrapping_mul),
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@ -71,13 +81,12 @@ where
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SL => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
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SR => self.binary_op(|l, r| u64::wrapping_shr(l, r as u32)),
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SRS => self.binary_op(|l: u64, r| i64::wrapping_shl(l as i64, r as u32) as u64),
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CMP => {
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CMP => handler!(self, |OpsRRR(tg, a0, a1)| {
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// Compare a0 <=> a1
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// < → 0
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// > → 1
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// = → 2
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let OpsRRR(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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@ -86,10 +95,9 @@ where
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as i64
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+ 1,
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);
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}
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CMPU => {
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}),
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CMPU => handler!(self, |OpsRRR(tg, a0, a1)| {
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// Unsigned comparsion
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let OpsRRR(tg, a0, a1) = self.decode();
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self.write_reg(
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tg,
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self.read_reg(a0)
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@ -98,25 +106,22 @@ where
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as i64
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+ 1,
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);
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}
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NEG => {
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}),
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NEG => handler!(self, |OpsRR(tg, a0)| {
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// Bit negation
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let OpsRR(tg, a0) = self.decode();
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self.write_reg(tg, !self.read_reg(a0).cast::<u64>())
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}
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NOT => {
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}),
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NOT => handler!(self, |OpsRR(tg, a0)| {
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// Logical negation
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let OpsRR(tg, a0) = self.decode();
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self.write_reg(tg, u64::from(self.read_reg(a0).cast::<u64>() == 0));
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}
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DIR => {
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}),
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DIR => handler!(self, |OpsRRRR(dt, rt, a0, a1)| {
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// Fused Division-Remainder
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let OpsRRRR(dt, rt, a0, a1) = self.decode();
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let a0 = self.read_reg(a0).cast::<u64>();
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let a1 = self.read_reg(a1).cast::<u64>();
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self.write_reg(dt, a0.checked_div(a1).unwrap_or(u64::MAX));
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self.write_reg(rt, a0.checked_rem(a1).unwrap_or(u64::MAX));
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}
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}),
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ADDI => self.binary_op_imm(u64::wrapping_add),
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MULI => self.binary_op_imm(u64::wrapping_sub),
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ANDI => self.binary_op_imm::<u64>(ops::BitAnd::bitand),
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@ -125,8 +130,7 @@ where
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SLI => self.binary_op_ims(u64::wrapping_shl),
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SRI => self.binary_op_ims(u64::wrapping_shr),
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SRSI => self.binary_op_ims(i64::wrapping_shr),
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CMPI => {
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let OpsRRD(tg, a0, imm) = self.decode();
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CMPI => handler!(self, |OpsRRD(tg, a0, imm)| {
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self.write_reg(
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tg,
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self.read_reg(a0)
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@ -134,18 +138,15 @@ where
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.cmp(&Value::from(imm).cast::<i64>())
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as i64,
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);
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}
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CMPUI => {
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let OpsRRD(tg, a0, imm) = self.decode();
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}),
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CMPUI => handler!(self, |OpsRRD(tg, a0, imm)| {
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self.write_reg(tg, self.read_reg(a0).cast::<u64>().cmp(&imm) as i64);
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}
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CP => {
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let OpsRR(tg, a0) = self.decode();
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}),
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CP => handler!(self, |OpsRR(tg, a0)| {
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self.write_reg(tg, self.read_reg(a0));
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}
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SWA => {
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}),
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SWA => handler!(self, |OpsRR(r0, r1)| {
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// Swap registers
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let OpsRR(r0, r1) = self.decode();
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match (r0, r1) {
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(0, 0) => (),
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(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
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@ -156,36 +157,41 @@ where
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);
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}
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}
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}
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LI => {
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let OpsRD(tg, imm) = self.decode();
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}),
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LI => handler!(self, |OpsRD(tg, imm)| {
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self.write_reg(tg, imm);
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}
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LRA => {
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let OpsRRO(tg, reg, imm) = self.decode();
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self.write_reg(tg, self.rel_addr(reg, imm).get());
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}
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LD => {
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}),
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LRA => handler!(self, |OpsRRO(tg, reg, imm)| {
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self.write_reg(
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tg,
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(self.pc + self.read_reg(reg).cast::<u64>() + imm + 3_u16).get(),
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);
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}),
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LD => handler!(self, |OpsRRAH(dst, base, off, count)| {
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// Load. If loading more than register size, continue on adjecent registers
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let OpsRRAH(dst, base, off, count) = self.decode();
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self.load(dst, base, off, count)?;
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}
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ST => {
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}),
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ST => handler!(self, |OpsRRAH(dst, base, off, count)| {
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// Store. Same rules apply as to LD
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let OpsRRAH(dst, base, off, count) = self.decode();
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self.store(dst, base, off, count)?;
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}
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LDR => {
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let OpsRROH(dst, base, off, count) = self.decode();
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self.load(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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STR => {
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let OpsRROH(dst, base, off, count) = self.decode();
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self.store(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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}),
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LDR => handler!(self, |OpsRROH(dst, base, off, count)| {
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self.load(
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dst,
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base,
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u64::from(off).wrapping_add((self.pc + 3_u64).get()),
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count,
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)?;
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}),
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STR => handler!(self, |OpsRROH(dst, base, off, count)| {
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self.store(
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dst,
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base,
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u64::from(off).wrapping_add((self.pc + 3_u64).get()),
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count,
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)?;
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}),
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BMC => {
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const INS_SIZE: usize = size_of::<OpsRRH>() + 1;
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// Block memory copy
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match if let Some(copier) = &mut self.copier {
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// There is some copier, poll.
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@ -194,9 +200,6 @@ where
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// There is none, make one!
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let OpsRRH(src, dst, count) = self.decode();
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// So we are still on BMC on next cycle
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self.pc -= INS_SIZE;
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self.copier = Some(BlockCopier::new(
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Address::new(self.read_reg(src).cast()),
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Address::new(self.read_reg(dst).cast()),
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@ -211,21 +214,19 @@ where
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// We are done, shift program counter
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core::task::Poll::Ready(Ok(())) => {
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self.copier = None;
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self.pc += INS_SIZE;
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self.bump_pc::<OpsRRH>();
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}
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// Error, shift program counter (for consistency)
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// and yield error
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core::task::Poll::Ready(Err(e)) => {
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self.pc += INS_SIZE;
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return Err(e.into());
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}
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// Not done yet, proceed to next cycle
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core::task::Poll::Pending => (),
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}
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}
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BRC => {
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BRC => handler!(self, |OpsRRB(src, dst, count)| {
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// Block register copy
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let OpsRRB(src, dst, count) = self.decode();
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if src.checked_add(count).is_none() || dst.checked_add(count).is_none() {
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return Err(VmRunError::RegOutOfBounds);
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}
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@ -235,89 +236,83 @@ where
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self.registers.get_unchecked_mut(usize::from(dst)),
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usize::from(count),
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);
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}
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JMP => self.pc = self.pc.wrapping_add(self.decode::<OpO>()),
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JAL => {
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}),
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JMP => handler!(self, |OpsO(off)| self.pc = self.pc.wrapping_add(off)),
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JAL => handler!(self, |OpsRRW(save, reg, offset)| {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg + offset.
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let OpsRRW(save, reg, offset) = self.decode();
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self.write_reg(save, self.pc.get());
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self.pc = Address::new(
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self.read_reg(reg).cast::<u64>().wrapping_add(offset.into()),
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);
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}
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}),
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// Conditional jumps, jump only to immediates
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JEQ => self.cond_jmp::<u64>(Ordering::Equal),
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JNE => {
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let OpsRRP(a0, a1, ja) = self.decode();
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JNE => handler!(self, |OpsRRP(a0, a1, ja)| {
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if self.read_reg(a0).cast::<u64>() != self.read_reg(a1).cast::<u64>() {
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self.pc = Address::new(
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((self.pc.get() as i64).wrapping_add(ja as i64)) as u64,
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)
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}
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}
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}),
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JLT => self.cond_jmp::<u64>(Ordering::Less),
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JGT => self.cond_jmp::<u64>(Ordering::Greater),
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JLTU => self.cond_jmp::<i64>(Ordering::Less),
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JGTU => self.cond_jmp::<i64>(Ordering::Greater),
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ECA => {
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self.decode::<()>();
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// So we don't get timer interrupt after ECALL
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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}
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self.bump_pc::<OpsN>();
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return Ok(VmRunOk::Ecall);
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}
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EBP => {
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self.decode::<()>();
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self.bump_pc::<OpsN>();
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return Ok(VmRunOk::Breakpoint);
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}
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ADDF => self.binary_op::<f64>(ops::Add::add),
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SUBF => self.binary_op::<f64>(ops::Sub::sub),
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MULF => self.binary_op::<f64>(ops::Mul::mul),
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DIRF => {
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let OpsRRRR(dt, rt, a0, a1) = self.decode();
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DIRF => handler!(self, |OpsRRRR(dt, rt, a0, a1)| {
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let a0 = self.read_reg(a0).cast::<f64>();
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let a1 = self.read_reg(a1).cast::<f64>();
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self.write_reg(dt, a0 / a1);
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self.write_reg(rt, a0 % a1);
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}
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FMAF => {
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let OpsRRRR(dt, a0, a1, a2) = self.decode();
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}),
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FMAF => handler!(self, |OpsRRRR(dt, a0, a1, a2)| {
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self.write_reg(
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dt,
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self.read_reg(a0).cast::<f64>() * self.read_reg(a1).cast::<f64>()
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+ self.read_reg(a2).cast::<f64>(),
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);
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}
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NEGF => {
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let OpsRR(dt, a0) = self.decode();
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}),
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NEGF => handler!(self, |OpsRR(dt, a0)| {
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self.write_reg(dt, -self.read_reg(a0).cast::<f64>());
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}
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ITF => {
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let OpsRR(dt, a0) = self.decode();
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}),
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ITF => handler!(self, |OpsRR(dt, a0)| {
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self.write_reg(dt, self.read_reg(a0).cast::<i64>() as f64);
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}
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}),
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FTI => {
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let OpsRR(dt, a0) = self.decode();
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self.write_reg(dt, self.read_reg(a0).cast::<f64>() as i64);
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}
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ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
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MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
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LRA16 => {
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let OpsRRP(tg, reg, imm) = self.decode();
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self.write_reg(tg, self.rel_addr(reg, imm).get());
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}
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LDR16 => {
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let OpsRRPH(dst, base, off, count) = self.decode();
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LRA16 => handler!(self, |OpsRRP(tg, reg, imm)| {
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self.write_reg(
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tg,
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(self.pc + self.read_reg(reg).cast::<u64>() + imm + 3_u16).get(),
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);
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}),
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LDR16 => handler!(self, |OpsRRPH(dst, base, off, count)| {
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self.load(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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STR16 => {
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let OpsRRPH(dst, base, off, count) = self.decode();
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}),
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STR16 => handler!(self, |OpsRRPH(dst, base, off, count)| {
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self.store(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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JMPR16 => self.pc = self.pc.wrapping_add(self.decode::<OpP>()),
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}),
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JMPR16 => handler!(self, |OpsP(off)| self.pc = self.pc.wrapping_add(off)),
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op => return Err(VmRunError::InvalidOpcode(op)),
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}
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}
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@ -331,13 +326,16 @@ where
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}
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}
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/// Bump instruction pointer
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#[inline(always)]
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fn bump_pc<T: BytecodeItem>(&mut self) {
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self.pc = self.pc.wrapping_add(core::mem::size_of::<T>() + 1);
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}
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/// Decode instruction operands
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#[inline(always)]
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unsafe fn decode<T: BytecodeItem>(&mut self) -> T {
|
||||
let pc1 = self.pc + 1_u64;
|
||||
let data = self.memory.prog_read_unchecked::<T>(pc1 as _);
|
||||
self.pc += 1 + size_of::<T>();
|
||||
data
|
||||
self.memory.prog_read_unchecked::<T>(self.pc + 1_u64)
|
||||
}
|
||||
|
||||
/// Load
|
||||
|
|
@ -391,6 +389,7 @@ where
|
|||
tg,
|
||||
op(self.read_reg(a0).cast::<T>(), self.read_reg(a1).cast::<T>()),
|
||||
);
|
||||
self.bump_pc::<OpsRRR>();
|
||||
}
|
||||
|
||||
/// Perform binary operation over register and immediate
|
||||
|
|
@ -401,6 +400,7 @@ where
|
|||
tg,
|
||||
op(self.read_reg(reg).cast::<T>(), Value::from(imm).cast::<T>()),
|
||||
);
|
||||
self.bump_pc::<OpsRRD>();
|
||||
}
|
||||
|
||||
/// Perform binary operation over register and shift immediate
|
||||
|
|
@ -408,14 +408,7 @@ where
|
|||
unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
|
||||
let OpsRRW(tg, reg, imm) = self.decode();
|
||||
self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
|
||||
}
|
||||
|
||||
/// Compute address relative to program counter an register value
|
||||
#[inline(always)]
|
||||
fn rel_addr(&self, reg: u8, imm: impl AddressOp) -> Address {
|
||||
self.pc
|
||||
.wrapping_add(self.read_reg(reg).cast::<u64>())
|
||||
.wrapping_add(imm)
|
||||
self.bump_pc::<OpsRRW>();
|
||||
}
|
||||
|
||||
/// Jump at `PC + #3` if ordering on `#0 <=> #1` is equal to expected
|
||||
|
|
@ -430,6 +423,8 @@ where
|
|||
{
|
||||
self.pc = Address::new(((self.pc.get() as i64).wrapping_add(ja as i64)) as u64);
|
||||
}
|
||||
|
||||
self.bump_pc::<OpsRRP>();
|
||||
}
|
||||
|
||||
/// Read register
|
||||
|
|
|
|||
Loading…
Reference in New Issue