From 7fa6a4524790f26c14018420f2e1505b861379a8 Mon Sep 17 00:00:00 2001
From: Erin <erin@erindesu.cz>
Date: Wed, 2 Feb 2022 00:06:00 +0100
Subject: [PATCH] cpuid fixed

---
 ableos/src/experiments/info.rs | 32 ++++++++++++++++----------------
 ableos/src/lib.rs              |  9 +++------
 2 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/ableos/src/experiments/info.rs b/ableos/src/experiments/info.rs
index fc6aec080..901a3d4f5 100644
--- a/ableos/src/experiments/info.rs
+++ b/ableos/src/experiments/info.rs
@@ -18,6 +18,7 @@
 //! }
 //! ```
 
+use core::arch::asm;
 use core::ops::Deref;
 use core::{fmt, slice, str};
 
@@ -39,28 +40,27 @@ pub enum RequestType {
 }
 
 pub fn cpuid(code: RequestType) -> (u32, u32, u32, u32) {
-    let res1;
-    let res2;
-    let res3;
-    let res4;
+    let eax;
+    let ebx;
+    let ecx;
+    let edx;
 
     unsafe {
-        llvm_asm!("cpuid"
-        : // output operands
-        "={eax}"(res1),
-        "={ebx}"(res2),
-        "={ecx}"(res3),
-        "={edx}"(res4)
-        : // input operands
-        "{eax}"(code as u32),
-        "{ecx}"(0 as u32)
-        : // clobbers
-        : // options
+        asm!(
+            "movq %rbx, {0:r}",
+            "cpuid",
+            "xchgq %rbx, {0:r}",
+            lateout(reg) ebx,
+            inlateout("eax") code as u32 => eax,
+            inlateout("ecx") 0 => ecx,
+            lateout("edx") edx,
+            options(nostack, preserves_flags, att_syntax),
         );
     }
 
-    (res1, res2, res3, res4)
+    (eax, ebx, ecx, edx)
 }
+
 /// The main entrypoint to the CPU information
 #[cfg(any(target_arch = "x86_64", target_arch = "x86"))]
 pub fn master() -> Option<Master> {
diff --git a/ableos/src/lib.rs b/ableos/src/lib.rs
index b3d9c2cad..d241fa5f3 100644
--- a/ableos/src/lib.rs
+++ b/ableos/src/lib.rs
@@ -6,17 +6,14 @@
 #![no_std]
 #![feature(
     abi_x86_interrupt,
-    // asm,
     asm_sym,
     alloc_error_handler,
     core_intrinsics,
-    // global_asm,
+    exclusive_range_pattern,
     lang_items,
-    llvm_asm,
-    naked_functions
+    naked_functions,
+    slice_pattern,
 )]
-#![feature(exclusive_range_pattern)]
-#![feature(slice_pattern)]
 
 /// Contains architecture specific code for aarch64.
 #[cfg(target_arch = "aarch64")]