ableos-idl/ableos/src/devices/pci_inner.rs

//! map the DeviceClass via <https://pci-ids.ucw.cz/read/PD>

use pci::PortOps;
#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
pub enum DeviceClass {
    UnclassifiedDevice = 0,
    MassStorageController = 0x01,
    NetworkController = 0x02,
    DisplayController = 0x03,
    MultimediaController = 0x04,
    MemoryController = 0x05,
    BridgeDevice = 0x06,

    CommunicationController = 0x07,
    GenericSystemPeripheral = 0x08,
    InputDevice = 0x09,
    DockingStation = 0x0a,
    Processor = 0x0b,
    SerialBusController = 0x0c,
    WirelessController = 0x0d,
    IntelligentController = 0x0e,
    SatelliteCommunicationController = 0x0f,
    EncryptionController = 0x10,
    SignalProcessingController = 0x11,

    // 14
    // 15
    // 16
    Coprocessor = 40,
    // 64
}

impl DeviceClass {
    pub fn from_u8(val: u8) -> DeviceClass {
        match val {
            0x00 => DeviceClass::UnclassifiedDevice,
            0x01 => DeviceClass::MassStorageController,
            0x02 => DeviceClass::NetworkController,
            0x03 => DeviceClass::DisplayController,
            0x04 => DeviceClass::MultimediaController,
            0x05 => DeviceClass::MemoryController,
            0x06 => DeviceClass::BridgeDevice,
            0x07 => DeviceClass::CommunicationController,
            0x08 => DeviceClass::GenericSystemPeripheral,
            0x09 => DeviceClass::InputDevice,
            0x0a => DeviceClass::DockingStation,
            0x0b => DeviceClass::Processor,
            0x0c => DeviceClass::SerialBusController,
            0x0d => DeviceClass::WirelessController,
            0x0e => DeviceClass::IntelligentController,
            0x0f => DeviceClass::SatelliteCommunicationController,
            0x10 => DeviceClass::EncryptionController,
            0x11 => DeviceClass::SignalProcessingController,
            0x40 => DeviceClass::Coprocessor,
            _ => DeviceClass::UnclassifiedDevice,
        }
    }
}

pub struct PciIO {}

impl PortOps for PciIO {
    unsafe fn read8(&self, port: u16) -> u8 {
        cpuio::inb(port as u16)
    }

    unsafe fn read16(&self, port: u16) -> u16 {
        cpuio::inw(port as u16)
    }

    unsafe fn read32(&self, port: u16) -> u32 {
        cpuio::inl(port as u16)
    }

    unsafe fn write8(&self, port: u16, val: u8) {
        cpuio::outb(val, port as u16);
    }

    unsafe fn write16(&self, port: u16, val: u16) {
        cpuio::outw(val, port as u16);
    }

    unsafe fn write32(&self, port: u16, val: u32) {
        cpuio::outl(val, port as u16);
    }
}