kodin/ableos-idl
1
0
Fork 0
forked from AbleOS/ableos
Code Pull requests Activity

Merge pull request 'Migrated to asm! macro and updated to fork of cpuio (which uses asm! instead of llvm_asm! too)' (#8) from assembly-fixes into master

Browse source 
Reviewed-on: https://git.ablecorp.us:443/able/ableos/pulls/8
This commit is contained in:
able 2022-02-02 03:51:09 +00:00
parent 3b9a3ab18a a60349c2f9
commit 016e94fedf
4 changed files with 22 additions and 25 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
ableos/Cargo.lock generated
View file

@ -150,8 +150,8 @@ dependencies = [
[[package]] [[package]]
name = "cpuio" name = "cpuio"
version = "0.3.0" version = "0.3.2"
source = "git+https://github.com/anyusernameworks/cpuio.git#3908ecab79df80670ee1c5121870fc131f07627b" source = "git+https://git.ablecorp.us/ondra05/cpuio.git#093cc103101b4ba4abd02d77c884113a376cdc64"
[[package]] [[package]]
name = "crunchy" name = "crunchy"

2
ableos/Cargo.toml
View file

@ -100,7 +100,7 @@ git = "https://git.ablecorp.us:443/able/externc-libm.git"
[target.'cfg(target_arch = "x86_64")'.dependencies] [target.'cfg(target_arch = "x86_64")'.dependencies]
bootloader = { version = "0.9.8", features = ["map_physical_memory"] } bootloader = { version = "0.9.8", features = ["map_physical_memory"] }
cpuio = { git = "https://github.com/anyusernameworks/cpuio.git" } cpuio = { git = "https://git.ablecorp.us/ondra05/cpuio.git" }
pic8259 = "0.10.1" pic8259 = "0.10.1"
uart_16550 = "0.2.0" uart_16550 = "0.2.0"
volatile = "0.2.6" volatile = "0.2.6"

32
ableos/src/experiments/info.rs
View file

@ -18,6 +18,7 @@
//! } //! }
//! ``` //! ```
use core::arch::asm;
use core::ops::Deref; use core::ops::Deref;
use core::{fmt, slice, str}; use core::{fmt, slice, str};
@ -39,28 +40,27 @@ pub enum RequestType {
} }
pub fn cpuid(code: RequestType) -> (u32, u32, u32, u32) { pub fn cpuid(code: RequestType) -> (u32, u32, u32, u32) {
let res1; let eax;
let res2; let ebx;
let res3; let ecx;
let res4; let edx;
unsafe { unsafe {
llvm_asm!("cpuid" asm!(
: // output operands "movq %rbx, {0:r}",
"={eax}"(res1), "cpuid",
"={ebx}"(res2), "xchgq %rbx, {0:r}",
"={ecx}"(res3), lateout(reg) ebx,
"={edx}"(res4) inlateout("eax") code as u32 => eax,
: // input operands inlateout("ecx") 0 => ecx,
"{eax}"(code as u32), lateout("edx") edx,
"{ecx}"(0 as u32) options(nostack, preserves_flags, att_syntax),
: // clobbers
: // options
); );
} }
(res1, res2, res3, res4) (eax, ebx, ecx, edx)
} }
/// The main entrypoint to the CPU information /// The main entrypoint to the CPU information
#[cfg(any(target_arch = "x86_64", target_arch = "x86"))] #[cfg(any(target_arch = "x86_64", target_arch = "x86"))]
pub fn master() -> Option<Master> { pub fn master() -> Option<Master> {

9
ableos/src/lib.rs
View file

@ -6,17 +6,14 @@
#![no_std] #![no_std]
#![feature( #![feature(
abi_x86_interrupt, abi_x86_interrupt,
// asm,
asm_sym, asm_sym,
alloc_error_handler, alloc_error_handler,
core_intrinsics, core_intrinsics,
// global_asm, exclusive_range_pattern,
lang_items, lang_items,
llvm_asm, naked_functions,
naked_functions slice_pattern,
)] )]
#![feature(exclusive_range_pattern)]
#![feature(slice_pattern)]
/// Contains architecture specific code for aarch64. /// Contains architecture specific code for aarch64.
#[cfg(target_arch = "aarch64")] #[cfg(target_arch = "aarch64")]