tests pass again

This commit is contained in:
mlokr 2024-06-23 09:26:03 +02:00
parent fe73f2d70f
commit 18d2d0fef3

View file

@ -1793,20 +1793,11 @@ impl Codegen {
} }
let lsize = self.tys.size_of(left.ty); let lsize = self.tys.size_of(left.ty);
let ty = ctx.ty.unwrap_or(left.ty);
let lhs = match ctx.loc.take() { let lhs = if left.loc.is_ref() && matches!(right, E::Number { .. }) {
Some(Loc::Rt { reg, .. }) self.loc_to_reg(&left.loc, lsize)
if matches!(&left.loc, Loc::Rt { reg: r, ..} if *r == reg) } else {
&& reg.get() != 1 => self.loc_to_reg(left.loc, lsize)
{
reg
}
Some(loc) => {
ctx = Ctx::from(Value { ty, loc });
self.loc_to_reg(left.loc, lsize)
}
None => self.loc_to_reg(left.loc, lsize),
}; };
let right = self.expr_ctx(right, Ctx::default().with_ty(left.ty))?; let right = self.expr_ctx(right, Ctx::default().with_ty(left.ty))?;
let rsize = self.tys.size_of(right.ty); let rsize = self.tys.size_of(right.ty);
@ -2216,14 +2207,14 @@ impl Codegen {
} }
} }
fn loc_to_reg(&mut self, loc: Loc, size: Size) -> reg::Id { fn loc_to_reg(&mut self, loc: impl Into<LocCow>, size: Size) -> reg::Id {
match loc { match loc.into() {
Loc::Rt { LocCow::Owned(Loc::Rt {
derefed: false, derefed: false,
mut reg, mut reg,
offset, offset,
stack, stack,
} => { }) => {
debug_assert!(stack.is_none(), "TODO"); debug_assert!(stack.is_none(), "TODO");
assert_eq!(offset, 0, "TODO"); assert_eq!(offset, 0, "TODO");
if reg.is_ref() { if reg.is_ref() {
@ -2233,12 +2224,22 @@ impl Codegen {
} }
reg reg
} }
Loc::Rt { .. } => { LocCow::Ref(&Loc::Rt {
derefed: false,
ref reg,
offset,
ref stack,
}) => {
debug_assert!(stack.is_none(), "TODO");
assert_eq!(offset, 0, "TODO");
reg.as_ref()
}
loc @ (LocCow::Ref(Loc::Rt { .. }) | LocCow::Owned(Loc::Rt { .. })) => {
let reg = self.ci.regs.allocate(); let reg = self.ci.regs.allocate();
self.store_sized(loc, Loc::reg(reg.as_ref()), size); self.store_sized(loc, Loc::reg(reg.as_ref()), size);
reg reg
} }
Loc::Ct { value } => { LocCow::Ref(&Loc::Ct { value }) | LocCow::Owned(Loc::Ct { value }) => {
let reg = self.ci.regs.allocate(); let reg = self.ci.regs.allocate();
self.output.emit(li64(reg.get(), u64::from_ne_bytes(value))); self.output.emit(li64(reg.get(), u64::from_ne_bytes(value)));
reg reg