forked from AbleOS/ableos
Spec update
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@ -54,18 +54,18 @@
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0x35, ANDI, RRD, "Bitand with immediate" ;
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0x36, ORI, RRD, "Bitor with immediate" ;
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0x37, XORI, RRD, "Bitxor with immediate" ;
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0x38, SLUI8, RRW, "Unsigned left bitshift with immedidate (8b)" ;
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0x39, SLUI16, RRW, "Unsigned left bitshift with immedidate (16b)";
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0x3A, SLUI32, RRW, "Unsigned left bitshift with immedidate (32b)";
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0x3B, SLUI64, RRW, "Unsigned left bitshift with immedidate (64b)";
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0x3C, SRUI8, RRW, "Unsigned right bitshift with immediate (8b)" ;
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0x3D, SRUI16, RRW, "Unsigned right bitshift with immediate (16b)";
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0x3E, SRUI32, RRW, "Unsigned right bitshift with immediate (32b)";
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0x3F, SRUI64, RRW, "Unsigned right bitshift with immediate (64b)";
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0x40, SRSI8, RRW, "Signed right bitshift with immediate" ;
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0x41, SRSI16, RRW, "Signed right bitshift with immediate" ;
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0x42, SRSI32, RRW, "Signed right bitshift with immediate" ;
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0x43, SRSI64, RRW, "Signed right bitshift with immediate" ;
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0x38, SLUI8, RRB, "Unsigned left bitshift with immedidate (8b)" ;
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0x39, SLUI16, RRB, "Unsigned left bitshift with immedidate (16b)";
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0x3A, SLUI32, RRB, "Unsigned left bitshift with immedidate (32b)";
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0x3B, SLUI64, RRB, "Unsigned left bitshift with immedidate (64b)";
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0x3C, SRUI8, RRB, "Unsigned right bitshift with immediate (8b)" ;
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0x3D, SRUI16, RRB, "Unsigned right bitshift with immediate (16b)";
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0x3E, SRUI32, RRB, "Unsigned right bitshift with immediate (32b)";
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0x3F, SRUI64, RRB, "Unsigned right bitshift with immediate (64b)";
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0x40, SRSI8, RRB, "Signed right bitshift with immediate" ;
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0x41, SRSI16, RRB, "Signed right bitshift with immediate" ;
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0x42, SRSI32, RRB, "Signed right bitshift with immediate" ;
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0x43, SRSI64, RRB, "Signed right bitshift with immediate" ;
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0x44, CMPUI, RRD, "Unsigned compare with immediate" ;
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0x45, CMPSI, RRD, "Signed compare with immediate" ;
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0x46, CP, RR, "Copy register" ;
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@ -85,17 +85,17 @@ where
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AND => self.binary_op::<u64>(ops::BitAnd::bitand),
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OR => self.binary_op::<u64>(ops::BitOr::bitor),
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XOR => self.binary_op::<u64>(ops::BitXor::bitxor),
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SLU8 => self.binary_op(|l, r| u8::wrapping_shl(l, r as u32)),
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SLU16 => self.binary_op(|l, r| u16::wrapping_shl(l, r as u32)),
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SLU32 => self.binary_op(u32::wrapping_shl),
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SLU64 => self.binary_op(|l, r| u64::wrapping_shl(l, r as u32)),
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SRU8 => self.binary_op(|l, r| u8::wrapping_shr(l, r as u32)),
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SRU16 => self.binary_op(|l, r| u16::wrapping_shr(l, r as u32)),
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SRU32 => self.binary_op(u32::wrapping_shr),
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SRS8 => self.binary_op(|l: i8, r| i8::wrapping_shl(l, r as u32)),
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SRS16 => self.binary_op(|l: i16, r| i16::wrapping_shl(l, r as u32)),
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SRS32 => self.binary_op(|l: i32, r| i32::wrapping_shl(l, r as u32)),
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SRS64 => self.binary_op(|l: i64, r| i64::wrapping_shl(l, r as u32)),
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SLU8 => self.binary_op::<u8>(ops::Shl::shl),
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SLU16 => self.binary_op::<u16>(ops::Shl::shl),
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SLU32 => self.binary_op::<u32>(ops::Shl::shl),
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SLU64 => self.binary_op::<u64>(ops::Shl::shl),
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SRU8 => self.binary_op::<u8>(ops::Shr::shr),
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SRU16 => self.binary_op::<u16>(ops::Shr::shr),
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SRU32 => self.binary_op::<u32>(ops::Shr::shr),
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SRS8 => self.binary_op::<u64>(ops::Shr::shr),
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SRS16 => self.binary_op::<i8>(ops::Shr::shr),
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SRS32 => self.binary_op::<i16>(ops::Shr::shr),
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SRS64 => self.binary_op::<i64>(ops::Shr::shr),
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CMPU => handler!(self, |OpsRRR(tg, a0, a1)| self.cmp(
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tg,
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a0,
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@ -459,8 +459,8 @@ where
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/// Perform binary operation over register and shift immediate
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#[inline(always)]
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unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u32) -> T) {
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let OpsRRW(tg, reg, imm) = self.decode();
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unsafe fn binary_op_ims<T: ValueVariant>(&mut self, op: impl Fn(T, u8) -> T) {
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let OpsRRB(tg, reg, imm) = self.decode();
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self.write_reg(tg, op(self.read_reg(reg).cast::<T>(), imm));
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self.bump_pc::<OpsRRW, true>();
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}
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30
spec.md
30
spec.md
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@ -28,10 +28,13 @@
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- Xi*n*: Sign-agnostic integer of size *n* bits (Xi8, Xi16, Xi32, Xi64)
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- Fl*n*: Floating point number of size *n* bits (Fl32, Fl64)
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# Behaviours
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- Integer operations are always wrapping, including signed numbers
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# Behaviour
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- Integer operations are wrapping, including signed numbers
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- Bitshifts are truncating
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- Two's complement
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- Floats as specified by IEEE 754
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- Execution model is implementation defined as long all observable
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effects are performed in correct order
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## Relative addressing
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Relative addresses are computed from address of the first byte
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@ -51,6 +54,25 @@ of offset in the code. Not from the beginning of current or following instructio
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| Towards +∞ (up) | 0b10 |
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| Towards -∞ (down) | 0b11 |
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- Remaining values in the byte traps with invalid operand exception
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# Memory
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- Memory implementation is implementation-defined
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- Zero address (`0x0`) is considered invalid
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# Traps
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- Environment call
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- Environment breakpoint
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Program counter goes to the following instruction
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## Exceptions
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- Memory access fault
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- Invalid operand
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- Unknown opcode
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Program counter stays on the currently executed instruction
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# Instructions
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- `#n`: register in parameter *n*
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- `$n`: for immediate in parameter *n*
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@ -210,6 +232,10 @@ of offset in the code. Not from the beginning of current or following instructio
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| 0x36 | ORI | Disjunction (\|) |
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| 0x37 | XORI | Non-equivalence (^) |
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# Register-immediate bitshifts
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- Type: `RRB`
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- Operation: `#0 ← #1 <OP> $2`
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## Unsigned left bitshift (`<<`)
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| Opcode | Mnemonic | Type |
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|:-------|:---------|:-----|
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