holey-bytes/lang/tests/son_tests_intcast_store.txt

main:
    ADDI64 r254, r254, -32d
    ST r31, r254, 16a, 16h
    ADDI64 r3, r254, 0d
    ADDI64 r2, r254, 8d
    LI64 r32, 0d
    ST r32, r254, 0a, 8h
    ST r32, r254, 8a, 8h
    LI64 r4, 1024d
    JAL r31, r0, :set
    ANDI r1, r1, 4294967295d
    LD r31, r254, 16a, 16h
    ADDI64 r254, r254, 32d
    JALA r0, r31, 0a
set:
    CP r1, r4
    JALA r0, r31, 0a
code size: 167
ret: 1024
status: Ok(())
forgot to mul by 8 2024-10-24 09:26:28 -05:00			`main:`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`ADDI64 r254, r254, -32d`
			`ST r31, r254, 16a, 16h`
saving this to make sure 2024-10-28 10:18:53 -05:00			`ADDI64 r3, r254, 0d`
adding rescheduling 2024-10-25 17:34:22 -05:00			`ADDI64 r2, r254, 8d`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`LI64 r32, 0d`
			`ST r32, r254, 0a, 8h`
			`ST r32, r254, 8a, 8h`
adding rescheduling 2024-10-25 17:34:22 -05:00			`LI64 r4, 1024d`
forgot to mul by 8 2024-10-24 09:26:28 -05:00			`JAL r31, r0, :set`
			`ANDI r1, r1, 4294967295d`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`LD r31, r254, 16a, 16h`
			`ADDI64 r254, r254, 32d`
forgot to mul by 8 2024-10-24 09:26:28 -05:00			`JALA r0, r31, 0a`
			`set:`
adding a lot better load elimination 2024-10-29 04:31:52 -05:00			`CP r1, r4`
forgot to mul by 8 2024-10-24 09:26:28 -05:00			`JALA r0, r31, 0a`
adding a lot better load elimination 2024-10-29 04:31:52 -05:00			`code size: 167`
forgot to mul by 8 2024-10-24 09:26:28 -05:00			`ret: 1024`
			`status: Ok(())`