holey-bytes/lang/tests/son_tests_if_statements.txt

fib:
    ADDI64 r254, r254, -40d
    ST r31, r254, 0a, 40h
    LI64 r1, 1d
    LI64 r32, 2d
    JGTU r2, r32, :0
    JMP :1
 0: CP r33, r2
    SUB64 r2, r33, r1
    CP r34, r33
    JAL r31, r0, :fib
    CP r2, r34
    CP r35, r1
    SUB64 r2, r2, r32
    JAL r31, r0, :fib
    ADD64 r1, r1, r35
 1: LD r31, r254, 0a, 40h
    ADDI64 r254, r254, 40d
    JALA r0, r31, 0a
main:
    ADDI64 r254, r254, -8d
    ST r31, r254, 0a, 8h
    LI64 r2, 10d
    JAL r31, r0, :fib
    LD r31, r254, 0a, 8h
    ADDI64 r254, r254, 8d
    JALA r0, r31, 0a
code size: 211
ret: 55
status: Ok(())
implementing optimizations up to is statements 2024-09-05 04:16:11 -05:00			`fib:`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`ADDI64 r254, r254, -40d`
			`ST r31, r254, 0a, 40h`
implementing optimizations up to is statements 2024-09-05 04:16:11 -05:00			`LI64 r1, 1d`
fixing report bug 2024-09-20 04:01:10 -05:00			`LI64 r32, 2d`
changing uint to be the default 2024-10-25 07:51:33 -05:00			`JGTU r2, r32, :0`
implementing optimizations up to is statements 2024-09-05 04:16:11 -05:00			`JMP :1`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`0: CP r33, r2`
			`SUB64 r2, r33, r1`
			`CP r34, r33`
implementing optimizations up to is statements 2024-09-05 04:16:11 -05:00			`JAL r31, r0, :fib`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`CP r2, r34`
			`CP r35, r1`
handling conditional stores 2024-10-18 06:11:11 -05:00			`SUB64 r2, r2, r32`
fixing report bug 2024-09-20 04:01:10 -05:00			`JAL r31, r0, :fib`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`ADD64 r1, r1, r35`
			`1: LD r31, r254, 0a, 40h`
			`ADDI64 r254, r254, 40d`
implementing optimizations up to is statements 2024-09-05 04:16:11 -05:00			`JALA r0, r31, 0a`
fixing report bug 2024-09-20 04:01:10 -05:00			`main:`
			`ADDI64 r254, r254, -8d`
			`ST r31, r254, 0a, 8h`
			`LI64 r2, 10d`
			`JAL r31, r0, :fib`
			`LD r31, r254, 0a, 8h`
			`ADDI64 r254, r254, 8d`
			`JALA r0, r31, 0a`
making a Backend trait to separate the different backends we will have in the fucture 2024-11-05 07:52:30 -06:00			`code size: 211`
implementing optimizations up to is statements 2024-09-05 04:16:11 -05:00			`ret: 55`
			`status: Ok(())`