forked from AbleOS/holey-bytes
Fixed bug + spec update
This commit is contained in:
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6fe1fd91bf
commit
1a53c80a62
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@ -154,6 +154,11 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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SR => binary_op!(self, as_u64, ops::Shr::shr),
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SR => binary_op!(self, as_u64, ops::Shr::shr),
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SRS => binary_op!(self, as_i64, ops::Shr::shr),
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SRS => binary_op!(self, as_i64, ops::Shr::shr),
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CMP => {
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CMP => {
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// Compare a0 <=> a1
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// < → -1
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// > → 1
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// = → 0
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let ParamBBB(tg, a0, a1) = param!(self, ParamBBB);
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let ParamBBB(tg, a0, a1) = param!(self, ParamBBB);
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self.write_reg(
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self.write_reg(
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tg,
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tg,
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@ -161,6 +166,7 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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);
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);
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}
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}
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CMPU => {
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CMPU => {
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// Unsigned comparsion
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let ParamBBB(tg, a0, a1) = param!(self, ParamBBB);
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let ParamBBB(tg, a0, a1) = param!(self, ParamBBB);
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self.write_reg(
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self.write_reg(
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tg,
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tg,
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@ -168,10 +174,12 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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);
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);
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}
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}
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NOT => {
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NOT => {
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// Logical negation
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let param = param!(self, ParamBB);
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let param = param!(self, ParamBB);
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self.write_reg(param.0, !self.read_reg(param.1).as_u64());
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self.write_reg(param.0, !self.read_reg(param.1).as_u64());
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}
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}
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NEG => {
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NEG => {
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// Bitwise negation
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let param = param!(self, ParamBB);
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let param = param!(self, ParamBB);
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self.write_reg(
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self.write_reg(
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param.0,
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param.0,
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@ -182,6 +190,7 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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);
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);
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}
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}
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DIR => {
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DIR => {
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// Fused Division-Remainder
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let ParamBBBB(dt, rt, a0, a1) = param!(self, ParamBBBB);
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let ParamBBBB(dt, rt, a0, a1) = param!(self, ParamBBBB);
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let a0 = self.read_reg(a0).as_u64();
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let a0 = self.read_reg(a0).as_u64();
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let a1 = self.read_reg(a1).as_u64();
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let a1 = self.read_reg(a1).as_u64();
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@ -212,12 +221,17 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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self.write_reg(param.0, self.read_reg(param.1));
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self.write_reg(param.0, self.read_reg(param.1));
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}
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}
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SWA => {
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SWA => {
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let ParamBB(src, dst) = param!(self, ParamBB);
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// Swap registers
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if src + dst != 0 {
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let ParamBB(r0, r1) = param!(self, ParamBB);
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core::ptr::swap(
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match (r0, r1) {
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self.registers.get_unchecked_mut(usize::from(src)),
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(0, 0) => (),
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self.registers.get_unchecked_mut(usize::from(dst)),
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(dst, 0) | (0, dst) => self.write_reg(dst, 0_u64),
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);
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(r0, r1) => {
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core::ptr::swap(
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self.registers.get_unchecked_mut(usize::from(r0)),
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self.registers.get_unchecked_mut(usize::from(r1)),
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);
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}
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}
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}
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}
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}
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LI => {
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LI => {
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@ -225,6 +239,7 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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self.write_reg(param.0, param.1);
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self.write_reg(param.0, param.1);
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}
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}
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LD => {
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LD => {
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// Load. If loading more than register size, continue on adjecent registers
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let ParamBBDH(dst, base, off, count) = param!(self, ParamBBDH);
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let ParamBBDH(dst, base, off, count) = param!(self, ParamBBDH);
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let n: usize = match dst {
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let n: usize = match dst {
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0 => 1,
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0 => 1,
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@ -239,6 +254,7 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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)?;
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)?;
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}
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}
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ST => {
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ST => {
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// Store. Same rules apply as to LD
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let ParamBBDH(dst, base, off, count) = param!(self, ParamBBDH);
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let ParamBBDH(dst, base, off, count) = param!(self, ParamBBDH);
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self.memory.store(
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self.memory.store(
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self.read_reg(base).as_u64() + off,
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self.read_reg(base).as_u64() + off,
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@ -248,6 +264,7 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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)?;
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)?;
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}
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}
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BMC => {
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BMC => {
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// Block memory copy
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let ParamBBD(src, dst, count) = param!(self, ParamBBD);
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let ParamBBD(src, dst, count) = param!(self, ParamBBD);
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self.memory.block_copy(
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self.memory.block_copy(
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self.read_reg(src).as_u64(),
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self.read_reg(src).as_u64(),
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@ -257,6 +274,7 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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)?;
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)?;
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}
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}
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BRC => {
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BRC => {
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// Block register copy
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let ParamBBB(src, dst, count) = param!(self, ParamBBB);
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let ParamBBB(src, dst, count) = param!(self, ParamBBB);
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core::ptr::copy(
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core::ptr::copy(
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self.registers.get_unchecked(usize::from(src)),
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self.registers.get_unchecked(usize::from(src)),
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@ -265,10 +283,13 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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);
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);
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}
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}
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JAL => {
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JAL => {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg + offset.
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let ParamBBD(save, reg, offset) = param!(self, ParamBBD);
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let ParamBBD(save, reg, offset) = param!(self, ParamBBD);
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self.write_reg(save, self.pc as u64);
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self.write_reg(save, self.pc as u64);
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self.pc = (self.read_reg(reg).as_u64() + offset) as usize;
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self.pc = (self.read_reg(reg).as_u64() + offset) as usize;
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}
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}
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// Conditional jumps, jump only to immediates
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JEQ => cond_jump!(self, int, Equal),
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JEQ => cond_jump!(self, int, Equal),
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JNE => {
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JNE => {
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let ParamBBD(a0, a1, jt) = param!(self, ParamBBD);
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let ParamBBD(a0, a1, jt) = param!(self, ParamBBD);
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@ -282,6 +303,11 @@ impl<'a, PfHandler: HandlePageFault, const TIMER_QUOTIENT: usize>
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JGTU => cond_jump!(self, sint, Greater),
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JGTU => cond_jump!(self, sint, Greater),
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ECALL => {
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ECALL => {
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param!(self, ());
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param!(self, ());
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// So we don't get timer interrupt after ECALL
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if TIMER_QUOTIENT != 0 {
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self.timer = self.timer.wrapping_add(1);
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}
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return Ok(VmRunOk::Ecall);
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return Ok(VmRunOk::Ecall);
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}
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}
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ADDF => binary_op!(self, as_f64, ops::Add::add),
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ADDF => binary_op!(self, as_f64, ops::Add::add),
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7
spec.md
7
spec.md
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@ -124,6 +124,9 @@
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### Swap
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### Swap
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- Type BB
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- Type BB
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- Swap #0 and #1
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- Swap #0 and #1
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- Zero register rules:
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- Both: no-op
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- One: Copy zero to the non-zero register
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:------:|
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|:------:|:----:|:------:|
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@ -263,8 +266,8 @@
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# Program execution
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# Program execution
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- The way of program execution is implementation defined
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- The way of program execution is implementation defined
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- The order of instruction is arbitrary, as long all observable
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- The execution is arbitrary, as long all effects are obervable
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effects are applied in the program's order
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in the way as program was executed literally, in order.
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# Program validation
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# Program validation
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- Invalid program should cause runtime error:
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- Invalid program should cause runtime error:
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