forked from AbleOS/holey-bytes
Changed CMP handling and added simple JMP
This commit is contained in:
parent
e7aa306e5d
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35f90e94a8
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@ -13,15 +13,15 @@
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static_assert(CHAR_BIT == 8, "Cursed architectures are not supported");
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static_assert(CHAR_BIT == 8, "Cursed architectures are not supported");
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enum hbbc_Opcode: uint8_t {
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enum hbbc_Opcode: uint8_t {
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hbbc_Op_UN , hbbc_Op_TX , hbbc_Op_NOP , hbbc_Op_ADD , hbbc_Op_SUB , hbbc_Op_MUL ,
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hbbc_Op_UN , hbbc_Op_TX , hbbc_Op_NOP , hbbc_Op_ADD , hbbc_Op_SUB , hbbc_Op_MUL ,
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hbbc_Op_AND , hbbc_Op_OR , hbbc_Op_XOR , hbbc_Op_SL , hbbc_Op_SR , hbbc_Op_SRS ,
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hbbc_Op_AND , hbbc_Op_OR , hbbc_Op_XOR , hbbc_Op_SL , hbbc_Op_SR , hbbc_Op_SRS ,
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hbbc_Op_CMP , hbbc_Op_CMPU , hbbc_Op_DIR , hbbc_Op_NEG , hbbc_Op_NOT , hbbc_Op_ADDI ,
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hbbc_Op_CMP , hbbc_Op_CMPU , hbbc_Op_DIR , hbbc_Op_NEG , hbbc_Op_NOT , hbbc_Op_ADDI ,
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hbbc_Op_MULI , hbbc_Op_ANDI , hbbc_Op_ORI , hbbc_Op_XORI , hbbc_Op_SLI , hbbc_Op_SRI ,
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hbbc_Op_MULI , hbbc_Op_ANDI , hbbc_Op_ORI , hbbc_Op_XORI , hbbc_Op_SLI , hbbc_Op_SRI ,
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hbbc_Op_SRSI , hbbc_Op_CMPI , hbbc_Op_CMPUI , hbbc_Op_CP , hbbc_Op_SWA , hbbc_Op_LI ,
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hbbc_Op_SRSI , hbbc_Op_CMPI , hbbc_Op_CMPUI , hbbc_Op_CP , hbbc_Op_SWA , hbbc_Op_LI ,
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hbbc_Op_LD , hbbc_Op_ST , hbbc_Op_BMC , hbbc_Op_BRC , hbbc_Op_JMP , hbbc_Op_JEQ ,
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hbbc_Op_LD , hbbc_Op_ST , hbbc_Op_BMC , hbbc_Op_BRC , hbbc_Op_JMP , hbbc_Op_JAL ,
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hbbc_Op_JNE , hbbc_Op_JLT , hbbc_Op_JGT , hbbc_Op_JLTU , hbbc_Op_JGTU , hbbc_Op_ECALL ,
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hbbc_Op_JEQ , hbbc_Op_JNE , hbbc_Op_JLT , hbbc_Op_JGT , hbbc_Op_JLTU , hbbc_Op_JGTU ,
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hbbc_Op_ADDF , hbbc_Op_SUBF , hbbc_Op_MULF , hbbc_Op_DIRF , hbbc_Op_FMAF , hbbc_Op_NEGF ,
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hbbc_Op_ECALL , hbbc_Op_ADDF , hbbc_Op_SUBF , hbbc_Op_MULF , hbbc_Op_DIRF , hbbc_Op_FMAF ,
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hbbc_Op_ITF , hbbc_Op_FTI , hbbc_Op_ADDFI , hbbc_Op_MULFI ,
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hbbc_Op_NEGF , hbbc_Op_ITF , hbbc_Op_FTI , hbbc_Op_ADDFI , hbbc_Op_MULFI ,
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} typedef hbbc_Opcode;
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} typedef hbbc_Opcode;
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static_assert(sizeof(hbbc_Opcode) == 1);
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static_assert(sizeof(hbbc_Opcode) == 1);
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@ -110,26 +110,27 @@ constmod!(pub opcode(u8) {
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BMC = 32, "BBD; [#0] ← [#1], imm #2 bytes";
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BMC = 32, "BBD; [#0] ← [#1], imm #2 bytes";
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BRC = 33, "BBB; #0 ← #1, imm #2 registers";
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BRC = 33, "BBB; #0 ← #1, imm #2 registers";
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JAL = 34, "BD; Copy PC to #0 and unconditional jump [#1 + imm #2]";
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JMP = 34, "D; Unconditional, non-linking absolute jump";
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JEQ = 35, "BBD; if #0 = #1 → jump imm #2";
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JAL = 35, "BD; Copy PC to #0 and unconditional jump [#1 + imm #2]";
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JNE = 36, "BBD; if #0 ≠ #1 → jump imm #2";
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JEQ = 36, "BBD; if #0 = #1 → jump imm #2";
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JLT = 37, "BBD; if #0 < #1 → jump imm #2";
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JNE = 37, "BBD; if #0 ≠ #1 → jump imm #2";
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JGT = 38, "BBD; if #0 > #1 → jump imm #2";
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JLT = 38, "BBD; if #0 < #1 → jump imm #2";
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JLTU = 39, "BBD; if #0 < #1 → jump imm #2 (unsigned)";
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JGT = 39, "BBD; if #0 > #1 → jump imm #2";
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JGTU = 40, "BBD; if #0 > #1 → jump imm #2 (unsigned)";
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JLTU = 40, "BBD; if #0 < #1 → jump imm #2 (unsigned)";
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ECALL = 41, "N; Issue system call";
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JGTU = 41, "BBD; if #0 > #1 → jump imm #2 (unsigned)";
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ECALL = 42, "N; Issue system call";
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ADDF = 42, "BBB; #0 ← #1 +. #2";
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ADDF = 43, "BBB; #0 ← #1 +. #2";
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SUBF = 43, "BBB; #0 ← #1 -. #2";
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SUBF = 44, "BBB; #0 ← #1 -. #2";
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MULF = 44, "BBB; #0 ← #1 +. #2";
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MULF = 45, "BBB; #0 ← #1 +. #2";
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DIRF = 45, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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DIRF = 46, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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FMAF = 46, "BBBB; #0 ← (#1 * #2) + #3";
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FMAF = 47, "BBBB; #0 ← (#1 * #2) + #3";
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NEGF = 47, "BB; #0 ← -#1";
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NEGF = 48, "BB; #0 ← -#1";
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ITF = 48, "BB; #0 ← #1 as float";
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ITF = 49, "BB; #0 ← #1 as float";
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FTI = 49, "BB; #0 ← #1 as int";
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FTI = 50, "BB; #0 ← #1 as int";
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ADDFI = 50, "BBD; #0 ← #1 +. imm #2";
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ADDFI = 51, "BBD; #0 ← #1 +. imm #2";
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MULFI = 51, "BBD; #0 ← #1 *. imm #2";
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MULFI = 52, "BBD; #0 ← #1 *. imm #2";
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});
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});
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#[repr(packed)]
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#[repr(packed)]
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@ -73,9 +73,9 @@ where
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SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
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SRS => self.binary_op(|l, r| i64::wrapping_shl(l, r as u32)),
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CMP => {
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CMP => {
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// Compare a0 <=> a1
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// Compare a0 <=> a1
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// < → -1
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// < → 0
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// > → 1
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// > → 1
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// = → 0
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// = → 2
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let ParamBBB(tg, a0, a1) = self.decode();
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let ParamBBB(tg, a0, a1) = self.decode();
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self.write_reg(
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self.write_reg(
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@ -83,7 +83,8 @@ where
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self.read_reg(a0)
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self.read_reg(a0)
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.cast::<i64>()
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.cast::<i64>()
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.cmp(&self.read_reg(a1).cast::<i64>())
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.cmp(&self.read_reg(a1).cast::<i64>())
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as i64,
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as i64
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+ 1,
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);
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);
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}
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}
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CMPU => {
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CMPU => {
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@ -94,7 +95,8 @@ where
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self.read_reg(a0)
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self.read_reg(a0)
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.cast::<u64>()
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.cast::<u64>()
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.cmp(&self.read_reg(a1).cast::<u64>())
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.cmp(&self.read_reg(a1).cast::<u64>())
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as i64,
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as i64
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+ 1,
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);
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);
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}
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}
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NOT => {
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NOT => {
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50
spec.md
50
spec.md
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@ -56,7 +56,7 @@
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| 7 | OR | Bitor |
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| 7 | OR | Bitor |
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| 8 | XOR | Bitxor |
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| 8 | XOR | Bitxor |
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| 9 | SL | Unsigned left bitshift |
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| 9 | SL | Unsigned left bitshift |
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| 10 | SR | Unsigned right bitshift |
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| 10 | SR | Unsigned right bitshift |
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| 11 | SRS | Signed right bitshift |
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| 11 | SRS | Signed right bitshift |
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### Comparsion
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### Comparsion
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@ -68,9 +68,9 @@
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#### Comparsion table
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#### Comparsion table
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| #1 *op* #2 | Result |
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| #1 *op* #2 | Result |
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|:----------:|:------:|
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|:----------:|:------:|
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| < | -1 |
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| < | 0 |
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| = | 0 |
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| = | 1 |
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| > | 1 |
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| > | 2 |
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### Division-remainder
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### Division-remainder
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- Type BBBB
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- Type BBBB
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@ -179,11 +179,17 @@
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## Control flow
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## Control flow
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### Unconditional jump
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### Unconditional jump
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- Type D
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------------------:|
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| 34 | JMP | Unconditional, non-linking jump |
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### Unconditional linking jump
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- Type BBD
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- Type BBD
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:--------------------------------------------------:|
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|:------:|:----:|:--------------------------------------------------:|
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| 34 | JAL | Save PC past JAL to `#0` and jump at `#1 + imm #2` |
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| 35 | JAL | Save PC past JAL to `#0` and jump at `#1 + imm #2` |
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### Conditional jumps
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### Conditional jumps
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- Type BBD
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- Type BBD
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@ -191,19 +197,19 @@
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| Opcode | Name | Comparsion |
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| Opcode | Name | Comparsion |
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|:------:|:----:|:------------:|
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|:------:|:----:|:------------:|
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| 35 | JEQ | = |
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| 36 | JEQ | = |
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| 36 | JNE | ≠ |
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| 37 | JNE | ≠ |
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| 37 | JLT | < (signed) |
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| 38 | JLT | < (signed) |
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| 38 | JGT | > (signed) |
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| 39 | JGT | > (signed) |
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| 39 | JLTU | < (unsigned) |
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| 40 | JLTU | < (unsigned) |
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| 40 | JGTU | > (unsigned) |
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| 41 | JGTU | > (unsigned) |
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### Environment call
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### Environment call
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- Type N
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- Type N
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------------------------:|
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|:------:|:-----:|:-------------------------------------:|
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| 41 | ECALL | Cause an trap to the host environment |
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| 42 | ECALL | Cause an trap to the host environment |
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## Floating point operations
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## Floating point operations
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- Type BBB
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- Type BBB
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@ -211,29 +217,29 @@
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:--------------:|
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|:------:|:----:|:--------------:|
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| 42 | ADDF | Addition |
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| 43 | ADDF | Addition |
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| 43 | SUBF | Subtraction |
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| 44 | SUBF | Subtraction |
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| 44 | MULF | Multiplication |
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| 45 | MULF | Multiplication |
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### Division-remainder
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### Division-remainder
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- Type BBBB
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- Type BBBB
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------------:|
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|:------:|:----:|:-------------------------:|
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| 45 | DIRF | Same as for integer `DIR` |
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| 46 | DIRF | Same as for integer `DIR` |
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### Fused Multiply-Add
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### Fused Multiply-Add
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- Type BBBB
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- Type BBBB
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:---------------------:|
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|:------:|:----:|:---------------------:|
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| 46 | FMAF | `#0 ← (#1 * #2) + #3` |
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| 47 | FMAF | `#0 ← (#1 * #2) + #3` |
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### Negation
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### Negation
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- Type BB
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- Type BB
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:----------:|
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|:------:|:----:|:----------:|
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| 47 | NEGF | `#0 ← -#1` |
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| 48 | NEGF | `#0 ← -#1` |
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### Conversion
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### Conversion
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- Type BB
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- Type BB
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@ -242,8 +248,8 @@
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:------------:|
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|:------:|:----:|:------------:|
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| 48 | ITF | Int to Float |
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| 49 | ITF | Int to Float |
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| 49 | FTI | Float to Int |
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| 50 | FTI | Float to Int |
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## Floating point immediate operations
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## Floating point immediate operations
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- Type BBD
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- Type BBD
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:-----:|:--------------:|
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|:------:|:-----:|:--------------:|
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| 50 | ADDFI | Addition |
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| 51 | ADDFI | Addition |
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| 51 | MULFI | Multiplication |
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| 52 | MULFI | Multiplication |
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# Registers
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# Registers
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- There is 255 registers + one zero register (with index 0)
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- There is 255 registers + one zero register (with index 0)
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