nah, lets use dummer code

This commit is contained in:
mlokr 2024-09-17 15:50:45 +02:00
parent bba3570788
commit 4a9b9de87f
No known key found for this signature in database
GPG key ID: DEA147DDEE644993
3 changed files with 70 additions and 37 deletions

View file

@ -1375,11 +1375,11 @@ impl Codegen {
Some(self.ci.inline_ret_loc.as_ref())
}
0 => None,
1..=16 => Some(Loc::reg(1)),
//9..=16 => None,
1..=8 => Some(Loc::reg(1)),
9..=16 => None,
_ => Some(Loc::reg(self.ci.ret_reg.as_ref()).into_derefed()),
};
//let loc_is_none = loc.is_none();
let loc_is_none = loc.is_none();
let value = if let Some(val) = val {
self.expr_ctx(val, Ctx { ty: self.ci.ret, loc })?
} else {
@ -1391,11 +1391,11 @@ impl Codegen {
Some(ret) => _ = self.assert_ty(pos, value.ty, ret, "return type"),
}
//if let 9..=16 = size
// && loc_is_none
//{
// self.store_sized(value.loc, Loc::reg(1), size);
//}
if let 9..=16 = size
&& loc_is_none
{
self.store_sized(value.loc, Loc::reg(1), size);
}
self.ci.ret_relocs.push(Reloc::new(self.ci.code.len(), 1, 4));
self.ci.emit(jmp(0));
@ -2286,25 +2286,25 @@ impl Codegen {
self.ci.emit(cp(dst.get(), src.get()));
}
}
(lpat!(false, src, 0, None), lpat!(false, dst, off, None)) => {
assert!(size <= 8);
let off_rem = 8 * (off % 8);
let freg = dst.get() + (off / 8) as u8;
if size < 8 {
let mask = !(((1u64 << (8 * size)) - 1) << off_rem);
self.ci.emit(andi(freg, freg, mask));
if off_rem == 0 {
self.ci.emit(or(freg, freg, src.get()));
} else {
let tmp = self.ci.regs.allocate();
self.ci.emit(slui64(tmp.get(), src.get(), off_rem as _));
self.ci.emit(or(freg, freg, src.get()));
self.ci.regs.free(tmp);
}
} else {
self.ci.emit(cp(freg, src.get()));
}
}
//(lpat!(false, src, 0, None), lpat!(false, dst, off, None)) => {
// assert!(size <= 8);
// let off_rem = 8 * (off % 8);
// let freg = dst.get() + (off / 8) as u8;
// if size < 8 {
// let mask = !(((1u64 << (8 * size)) - 1) << off_rem);
// self.ci.emit(andi(freg, freg, mask));
// if off_rem == 0 {
// self.ci.emit(or(freg, freg, src.get()));
// } else {
// let tmp = self.ci.regs.allocate();
// self.ci.emit(slui64(tmp.get(), src.get(), off_rem as _));
// self.ci.emit(or(freg, freg, src.get()));
// self.ci.regs.free(tmp);
// }
// } else {
// self.ci.emit(cp(freg, src.get()));
// }
//}
(lpat!(true, src, soff, ref ssta), lpat!(false, dst, 0, None)) => {
if size < 8 {
self.ci.emit(cp(dst.get(), 0));

View file

@ -22,16 +22,18 @@ main:
ADDI64 r254, r254, 40d
JALA r0, r31, 0a
foo:
ADDI64 r254, r254, -8d
ST r31, r254, 0a, 8h
LI64 r1, 3d
ANDI r2, r2, -4294967296d
ORI r2, r2, 2d
ANDI r2, r2, 4294967295d
ORI r2, r2, 8589934592d
LD r31, r254, 0a, 8h
ADDI64 r254, r254, 8d
ADDI64 r254, r254, -32d
ST r31, r254, 16a, 16h
LI64 r32, 3d
ST r32, r254, 0a, 8h
LI64 r32, 2d
ST r32, r254, 8a, 4h
LI64 r32, 2d
ST r32, r254, 12a, 4h
LD r1, r254, 0a, 16h
LD r31, r254, 16a, 16h
ADDI64 r254, r254, 32d
JALA r0, r31, 0a
code size: 313
code size: 341
ret: 0
status: Ok(())

View file

@ -0,0 +1,31 @@
main:
ADDI64 r254, r254, -48d
ST r31, r254, 16a, 32h
CP r32, r3
CP r33, r4
LI64 r34, 0d
ST r34, r254, 8a, 1h
LI64 r34, 0d
ST r34, r254, 9a, 1h
LI64 r34, 0d
ST r34, r254, 10a, 1h
LI64 r34, 0d
ST r34, r254, 11a, 1h
LI64 r34, 0d
ST r34, r254, 12a, 1h
LI64 r34, 0d
ST r34, r254, 13a, 1h
LI64 r34, 0d
ST r34, r254, 14a, 1h
LI64 r34, 0d
ST r34, r254, 15a, 1h
LD r34, r254, 8a, 8h
ST r34, r254, 0a, 8h
ST r34, r254, 8a, 8h
LD r1, r254, 0a, 16h
LD r31, r254, 16a, 32h
ADDI64 r254, r254, 48d
JALA r0, r31, 0a
code size: 309
ret: 0
status: Ok(())