forked from AbleOS/holey-bytes
Maybe fixed relative addressing bugs
This commit is contained in:
parent
b4923cfb95
commit
83563fff84
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@ -5,8 +5,8 @@ use core::convert::TryFrom;
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type OpR = u8;
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type OpA = u64;
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type OpO = u32;
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type OpP = u16;
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type OpO = i32;
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type OpP = i16;
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type OpB = u8;
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type OpH = u16;
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@ -112,11 +112,20 @@ pub trait AddressOp {
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fn cast_u64(self) -> u64;
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}
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macro_rules! impl_address_ops(($($ty:ty),* $(,)?) => {
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macro_rules! impl_address_ops_u(($($ty:ty),* $(,)?) => {
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$(impl AddressOp for $ty {
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#[inline(always)]
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fn cast_u64(self) -> u64 { self as _ }
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})*
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});
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impl_address_ops!(u8, u16, u32, u64, usize);
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macro_rules! impl_address_ops_i(($($ty:ty),* $(,)?) => {
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$(impl AddressOp for $ty {
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#[inline(always)]
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fn cast_u64(self) -> u64 { self as i64 as u64 }
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})*
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});
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impl_address_ops_u!(u8, u16, u32, u64, usize);
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impl_address_ops_i!(i8, i16, i32, i64, isize);
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@ -4,6 +4,8 @@
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use hbbytecode::RoundingMode;
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use crate::mem::addr::AddressOp;
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use {
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super::{
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bmc::BlockCopier,
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@ -201,10 +203,12 @@ where
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LI16 => handler!(self, |OpsRH(tg, imm)| self.write_reg(tg, imm)),
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LI32 => handler!(self, |OpsRW(tg, imm)| self.write_reg(tg, imm)),
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LI64 => handler!(self, |OpsRD(tg, imm)| self.write_reg(tg, imm)),
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LRA => handler!(self, |OpsRRO(tg, reg, imm)| {
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LRA => handler!(self, |OpsRRO(tg, reg, off)| {
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self.write_reg(
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tg,
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(self.pc + self.read_reg(reg).cast::<u64>() + imm + 3_u16).get(),
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self.pcrel(off, 3)
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.wrapping_add(self.read_reg(reg).cast::<i64>())
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.get(),
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);
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}),
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LD => handler!(self, |OpsRRAH(dst, base, off, count)| {
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@ -216,20 +220,10 @@ where
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self.store(dst, base, off, count)?;
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}),
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LDR => handler!(self, |OpsRROH(dst, base, off, count)| {
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self.load(
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dst,
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base,
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u64::from(off).wrapping_add((self.pc + 3_u64).get()),
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count,
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)?;
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self.load(dst, base, self.pcrel(off, 3).get(), count)?;
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}),
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STR => handler!(self, |OpsRROH(dst, base, off, count)| {
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self.store(
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dst,
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base,
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u64::from(off).wrapping_add((self.pc + 3_u64).get()),
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count,
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)?;
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self.store(dst, base, self.pcrel(off, 3).get(), count)?;
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}),
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BMC => {
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// Block memory copy
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@ -278,14 +272,13 @@ where
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);
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}),
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JMP => handler!(self, |OpsO(off)| self.pc = self.pc.wrapping_add(off)),
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JAL => handler!(self, |OpsRRW(save, reg, offset)| {
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JAL => handler!(self, |OpsRRO(save, reg, offset)| {
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// Jump and link. Save PC after this instruction to
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// specified register and jump to reg + relative offset.
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self.write_reg(save, self.pc.get());
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self.pc = self
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.pc
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.wrapping_add(self.read_reg(reg).cast::<u64>())
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.wrapping_add(offset);
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.pcrel(offset, 3)
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.wrapping_add(self.read_reg(reg).cast::<i64>());
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}),
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JALA => handler!(self, |OpsRRW(save, reg, offset)| {
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// Jump and link. Save PC after this instruction to
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@ -387,12 +380,12 @@ where
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);
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}),
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LDR16 => handler!(self, |OpsRRPH(dst, base, off, count)| {
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self.load(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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self.load(dst, base, self.pcrel(off, 3).get(), count)?;
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}),
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STR16 => handler!(self, |OpsRRPH(dst, base, off, count)| {
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self.store(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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self.store(dst, base, self.pcrel(off, 3).get(), count)?;
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}),
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JMP16 => handler!(self, |OpsP(off)| self.pc = self.pc.wrapping_add(off)),
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JMP16 => handler!(self, |OpsP(off)| self.pc = self.pcrel(off, 1)),
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op => return Err(VmRunError::InvalidOpcode(op)),
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}
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}
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@ -537,6 +530,12 @@ where
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});
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}
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/// Calculate pc-relative address
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#[inline(always)]
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fn pcrel(&self, offset: impl AddressOp, pos: u8) -> Address {
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self.pc.wrapping_add(pos).wrapping_add(offset)
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}
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/// Jump at `PC + #3` if ordering on `#0 <=> #1` is equal to expected
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#[inline(always)]
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unsafe fn cond_jmp<T: ValueVariant + Ord>(&mut self, expected: Ordering) {
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@ -547,7 +546,7 @@ where
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.cmp(&self.read_reg(a1).cast::<T>())
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== expected
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{
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self.pc = Address::new(((self.pc.get() as i64).wrapping_add(ja as i64)) as u64);
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self.pc = self.pcrel(ja, 3);
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}
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self.bump_pc::<OpsRRP, true>();
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