forked from AbleOS/holey-bytes
fixing the useles register alloc when loading
This commit is contained in:
parent
d64fa7e1f9
commit
8928888481
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@ -8,7 +8,7 @@ use {
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parser::{self, find_symbol, idfl, CtorField, Expr, ExprRef, FileId, Pos},
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HashMap,
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},
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std::{collections::BTreeMap, fmt::Display, ops::Range, rc::Rc, u32},
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std::{collections::BTreeMap, fmt::Display, ops::Range, rc::Rc},
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};
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type Offset = u32;
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@ -2209,8 +2209,8 @@ impl Codegen {
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},
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left.loc,
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)
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} else if left.loc.is_ref() {
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(self.loc_to_reg(&left.loc, lsize), dbg!(self.ci.regs.allocate()), left.loc)
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} else if left.loc.is_ref() && left.loc.is_reg() {
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(self.loc_to_reg(&left.loc, lsize), self.ci.regs.allocate(), left.loc)
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} else {
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let lhs = self.loc_to_reg(left.loc, lsize);
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(lhs.as_ref(), lhs, Loc::default())
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@ -15,14 +15,12 @@ use {
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core::fmt,
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std::{
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cell::RefCell,
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cmp,
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collections::{hash_map, BTreeMap},
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fmt::{Display, Write},
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hash::{Hash as _, Hasher},
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mem,
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ops::{self, Range},
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rc::Rc,
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u32,
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},
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};
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@ -34,21 +34,21 @@ main:
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JMP :1
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2: CP r33, r0
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LD r33, r254, 4a, 4h
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CP r34, r0
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LD r34, r254, 8a, 4h
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ADD32 r32, r33, r34
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CP r34, r0
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LD r34, r254, 0a, 1h
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ADD32 r32, r32, r34
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CP r34, r0
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LD r34, r254, 1a, 1h
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ADD32 r32, r32, r34
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CP r34, r0
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LD r34, r254, 2a, 1h
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ADD32 r32, r32, r34
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CP r34, r0
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LD r34, r254, 3a, 1h
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ADD32 r1, r32, r34
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CP r32, r0
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LD r32, r254, 8a, 4h
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ADD32 r33, r33, r32
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CP r32, r0
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LD r32, r254, 0a, 1h
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ADD32 r33, r33, r32
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CP r32, r0
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LD r32, r254, 1a, 1h
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ADD32 r33, r33, r32
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CP r32, r0
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LD r32, r254, 2a, 1h
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ADD32 r33, r33, r32
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CP r32, r0
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LD r32, r254, 3a, 1h
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ADD32 r1, r33, r32
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1: LD r31, r254, 12a, 32h
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ADDI64 r254, r254, 44d
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JALA r0, r31, 0a
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@ -18,19 +18,19 @@ main:
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ADDI64 r254, r254, 48d
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JALA r0, r31, 0a
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deinit:
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ADDI64 r254, r254, -32d
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ST r31, r254, 0a, 32h
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ADDI64 r254, r254, -24d
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ST r31, r254, 0a, 24h
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CP r32, r2
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LD r2, r32, 0a, 8h
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LD r33, r32, 16a, 8h
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MULI64 r34, r33, 8d
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CP r3, r34
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MULI64 r33, r33, 8d
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CP r3, r33
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LI64 r4, 8d
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JAL r31, r0, :free
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CP r1, r32
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JAL r31, r0, :new
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LD r31, r254, 0a, 32h
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ADDI64 r254, r254, 32d
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LD r31, r254, 0a, 24h
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ADDI64 r254, r254, 24d
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JALA r0, r31, 0a
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free:
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ADDI64 r254, r254, -40d
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@ -62,10 +62,10 @@ push:
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ST r34, r32, 16a, 8h
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JMP :2
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1: LD r34, r32, 16a, 8h
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MULI64 r35, r34, 2d
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ST r35, r32, 16a, 8h
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2: LD r35, r32, 16a, 8h
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MULI64 r34, r35, 8d
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MULI64 r34, r34, 2d
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ST r34, r32, 16a, 8h
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2: LD r34, r32, 16a, 8h
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MULI64 r34, r34, 8d
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CP r2, r34
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LI64 r3, 8d
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JAL r31, r0, :malloc
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@ -77,37 +77,37 @@ push:
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3: LD r35, r32, 0a, 8h
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CP r36, r34
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LD r37, r32, 0a, 8h
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LD r39, r32, 8a, 8h
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MULI64 r39, r39, 8d
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ADD64 r38, r37, r39
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7: JNE r35, r38, :5
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LD r38, r32, 8a, 8h
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MULI64 r38, r38, 8d
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ADD64 r37, r37, r38
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7: JNE r35, r37, :5
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JMP :6
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5: CP r39, r36
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CP r37, r35
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BMC r37, r39, 8h
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5: CP r38, r36
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CP r39, r35
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BMC r39, r38, 8h
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ADDI64 r35, r35, 8d
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ADDI64 r36, r36, 8d
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JMP :7
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6: LD r39, r32, 8a, 8h
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LI64 r37, 0d
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JEQ r39, r37, :8
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6: LD r38, r32, 8a, 8h
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LI64 r39, 0d
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JEQ r38, r39, :8
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LD r2, r32, 0a, 8h
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LD r37, r32, 8a, 8h
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MULI64 r39, r37, 8d
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LD r39, r32, 8a, 8h
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MULI64 r39, r39, 8d
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CP r3, r39
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LI64 r4, 8d
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JAL r31, r0, :free
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8: ST r34, r32, 0a, 8h
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0: LD r34, r32, 0a, 8h
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LD r37, r32, 8a, 8h
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MULI64 r37, r37, 8d
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ADD64 r39, r34, r37
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CP r37, r39
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ST r33, r37, 0a, 8h
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LD r37, r32, 8a, 8h
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ADDI64 r37, r37, 1d
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ST r37, r32, 8a, 8h
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CP r1, r39
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LD r39, r32, 8a, 8h
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MULI64 r39, r39, 8d
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ADD64 r34, r34, r39
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CP r39, r34
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ST r33, r39, 0a, 8h
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LD r39, r32, 8a, 8h
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ADDI64 r39, r39, 1d
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ST r39, r32, 8a, 8h
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CP r1, r34
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4: LD r31, r254, 0a, 72h
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ADDI64 r254, r254, 72d
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JALA r0, r31, 0a
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@ -114,16 +114,16 @@ rect_line:
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0: LD r34, r254, 8a, 8h
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LD r35, r254, 0a, 8h
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4: LD r36, r254, 8a, 8h
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LD r38, r254, 16a, 8h
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ADD64 r37, r36, r38
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JNE r34, r37, :2
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LD r37, r254, 16a, 8h
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ADD64 r36, r36, r37
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JNE r34, r36, :2
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JMP :3
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2: LI64 r37, 1d
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LI64 r38, 10d
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ADD64 r37, r37, r38
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LI64 r38, 1d
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LI64 r36, 2d
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ADD64 r37, r38, r36
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2: LI64 r36, 1d
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LI64 r37, 10d
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ADD64 r36, r36, r37
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LI64 r37, 1d
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LI64 r38, 2d
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ADD64 r36, r37, r38
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ADDI64 r34, r34, 1d
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JMP :4
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3: ADDI64 r33, r33, 1d
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