forked from AbleOS/holey-bytes
appliing late peepholes
This commit is contained in:
parent
b62413046d
commit
9095af6d84
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@ -23,10 +23,10 @@ use {
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cell::RefCell,
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fmt::{self, Debug, Display, Write},
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format_args as fa, mem,
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ops::{self, Deref},
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ops::{self, Deref, Not},
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},
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hashbrown::hash_map,
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hbbytecode::DisasmError,
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hbbytecode::{st, DisasmError},
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regalloc2::VReg,
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};
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@ -279,6 +279,36 @@ impl Nodes {
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true
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}
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fn late_peephole(&mut self, target: Nid) -> Option<Nid> {
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if let Some(id) = self.peephole(target) {
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self.replace(target, id);
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return Some(id);
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}
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None
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}
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fn iter_peeps(&mut self, mut fuel: usize) {
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let mut in_stack = BitSet::default();
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in_stack.clear(self.values.len());
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let mut stack =
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self.iter().map(|(id, ..)| id).inspect(|&id| _ = in_stack.set(id)).collect::<Vec<_>>();
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while fuel != 0
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&& let Some(node) = stack.pop()
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{
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fuel -= 1;
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in_stack.unset(node);
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let new = self.late_peephole(node);
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if let Some(new) = new {
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for &i in self[new].outputs.iter().chain(self[new].inputs.iter()) {
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if in_stack.set(i) {
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stack.push(i)
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}
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}
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}
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}
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}
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fn peephole(&mut self, target: Nid) -> Option<Nid> {
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use {Kind as K, TokenKind as T};
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match self[target].kind {
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@ -703,14 +733,6 @@ impl Nodes {
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}
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}
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fn late_peephole(&mut self, target: Nid) -> Nid {
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if let Some(id) = self.peephole(target) {
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self.replace(target, id);
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return id;
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}
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target
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}
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fn load_loop_var(&mut self, index: usize, value: &mut Variable, loops: &mut [Loop]) {
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self.load_loop_value(&mut |l| l.scope.iter_mut().nth(index).unwrap(), value, loops);
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}
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@ -1182,6 +1204,7 @@ impl ItemCtx {
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self.nodes.unlock(ENTRY);
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self.nodes.unlock(MEM);
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self.nodes.eliminate_stack_temporaries();
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self.nodes.iter_peeps(1000);
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}
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fn emit(&mut self, instr: (usize, [u8; instrs::MAX_SIZE])) {
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@ -1892,7 +1915,7 @@ impl<'a> Codegen<'a> {
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}
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let store = self.ci.nodes.new_node_nop(ty, Kind::Stre, vc);
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self.ci.scope.store.set_value(store, &mut self.ci.nodes);
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let opted = self.ci.nodes.late_peephole(store);
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let opted = self.ci.nodes.late_peephole(store).unwrap_or(store);
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self.ci.scope.store.set_value_remove(opted, &mut self.ci.nodes);
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opted
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}
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@ -2954,7 +2977,7 @@ impl<'a> Codegen<'a> {
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self.ci.nodes.unlock(self.ci.ctrl);
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self.ci.nodes.unlock(node);
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let rpl = self.ci.nodes.late_peephole(node);
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let rpl = self.ci.nodes.late_peephole(node).unwrap_or(node);
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if self.ci.ctrl == node {
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self.ci.ctrl = rpl;
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}
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@ -287,6 +287,15 @@ impl BitSet {
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self.data.resize(new_len, 0);
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}
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pub fn unset(&mut self, idx: Nid) -> bool {
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let idx = idx as usize;
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let data_idx = idx / Self::ELEM_SIZE;
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let sub_idx = idx % Self::ELEM_SIZE;
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let prev = self.data[data_idx] & (1 << sub_idx);
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self.data[data_idx] &= !(1 << sub_idx);
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prev != 0
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}
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pub fn set(&mut self, idx: Nid) -> bool {
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let idx = idx as usize;
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let data_idx = idx / Self::ELEM_SIZE;
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@ -1,17 +1,17 @@
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main:
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ADDI64 r254, r254, -128d
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LI8 r7, 69b
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LI64 r5, 128d
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LI64 r6, 0d
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LI64 r6, 128d
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LI64 r8, 0d
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ADDI64 r4, r254, 0d
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2: JLTU r6, r5, :0
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2: JLTU r8, r6, :0
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LD r3, r254, 42a, 1h
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ANDI r1, r3, 255d
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JMP :1
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0: ADDI64 r8, r6, 1d
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ADD64 r6, r6, r4
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ST r7, r6, 0a, 1h
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CP r6, r8
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0: ADDI64 r5, r8, 1d
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ADD64 r12, r4, r8
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ST r7, r12, 0a, 1h
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CP r8, r5
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JMP :2
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1: ADDI64 r254, r254, 128d
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JALA r0, r31, 0a
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@ -23,19 +23,19 @@ main:
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MUL64 r11, r11, r6
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MULI64 r9, r9, 8d
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ADD64 r11, r11, r10
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ADD64 r9, r9, r5
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ADD64 r9, r5, r9
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MULI64 r11, r11, 8d
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ADDI64 r10, r254, 32d
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ADD64 r12, r11, r5
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ADD64 r11, r5, r11
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BMC r9, r10, 8h
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BMC r12, r9, 8h
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BMC r10, r12, 8h
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BMC r11, r9, 8h
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BMC r10, r11, 8h
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CP r10, r3
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JMP :5
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0: ADD64 r2, r9, r8
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MULI64 r12, r9, 8d
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ADD64 r3, r12, r5
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ST r9, r3, 0a, 8h
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ADD64 r7, r5, r12
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ST r9, r7, 0a, 8h
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CP r9, r2
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JMP :6
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2: ADDI64 r254, r254, 40d
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@ -32,89 +32,87 @@ main:
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LD r11, r254, 150a, 1h
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ADD8 r1, r11, r10
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LD r3, r254, 148a, 1h
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ADD8 r6, r3, r1
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LD r7, r254, 151a, 1h
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LI8 r9, 4b
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ADD8 r11, r7, r6
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ANDI r11, r11, 255d
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ANDI r9, r9, 255d
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JEQ r11, r9, :0
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ADD8 r7, r3, r1
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LI8 r8, 4b
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ADD8 r7, r7, r6
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ANDI r7, r7, 255d
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ANDI r8, r8, 255d
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JEQ r7, r8, :0
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LI64 r1, 1008d
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JMP :1
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0: LI64 r5, 1d
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ADDI64 r8, r254, 80d
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ST r5, r254, 80a, 8h
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LI64 r9, 2d
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ST r9, r254, 88a, 8h
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LI64 r1, 3d
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ADDI64 r4, r254, 32d
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ST r1, r254, 32a, 8h
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LI64 r5, 4d
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ST r5, r254, 40a, 8h
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LD r12, r254, 32a, 8h
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LD r1, r254, 80a, 8h
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ADDI64 r11, r254, 0d
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ADD64 r3, r12, r1
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ST r3, r254, 0a, 8h
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LD r7, r254, 40a, 8h
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LD r9, r254, 88a, 8h
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ADD64 r10, r7, r9
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ST r10, r254, 8a, 8h
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LD r2, r254, 80a, 8h
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LD r3, r254, 32a, 8h
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SUB64 r5, r3, r2
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ST r5, r254, 16a, 8h
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LD r9, r254, 88a, 8h
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LD r10, r254, 40a, 8h
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SUB64 r12, r10, r9
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ST r12, r254, 24a, 8h
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ADDI64 r3, r254, 112d
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BMC r11, r3, 32h
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LI64 r6, 0d
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ADDI64 r9, r254, 96d
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ST r6, r254, 96a, 8h
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ST r6, r254, 104a, 8h
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LD r1, r254, 32a, 8h
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LD r2, r254, 96a, 8h
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ADDI64 r9, r254, 48d
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SUB64 r5, r2, r1
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ST r5, r254, 48a, 8h
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LD r10, r254, 40a, 8h
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LD r11, r254, 104a, 8h
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SUB64 r12, r11, r10
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ST r12, r254, 56a, 8h
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ADDI64 r10, r9, 16d
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BMC r8, r10, 16h
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LD r7, r254, 112a, 8h
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LD r8, r254, 48a, 8h
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ADD64 r10, r8, r7
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ST r10, r254, 48a, 8h
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LD r2, r254, 120a, 8h
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LD r3, r254, 56a, 8h
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ADD64 r5, r2, r3
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ST r5, r254, 56a, 8h
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LD r10, r254, 128a, 8h
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LD r11, r254, 64a, 8h
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0: LI64 r3, 1d
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ADDI64 r6, r254, 80d
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ST r3, r254, 80a, 8h
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LI64 r7, 2d
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ST r7, r254, 88a, 8h
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LI64 r11, 3d
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ADDI64 r2, r254, 32d
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ST r11, r254, 32a, 8h
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LI64 r3, 4d
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ST r3, r254, 40a, 8h
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LD r10, r254, 32a, 8h
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LD r11, r254, 80a, 8h
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ADDI64 r9, r254, 0d
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ADD64 r1, r10, r11
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ST r1, r254, 64a, 8h
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LD r5, r254, 136a, 8h
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LD r6, r254, 72a, 8h
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ADD64 r8, r5, r6
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ST r8, r254, 72a, 8h
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LD r12, r254, 64a, 8h
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LD r1, r254, 48a, 8h
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ADDI64 r7, r254, 152d
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ADD64 r4, r12, r1
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ST r4, r254, 152a, 8h
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LD r8, r254, 72a, 8h
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LD r9, r254, 56a, 8h
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ST r1, r254, 0a, 8h
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LD r5, r254, 40a, 8h
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LD r7, r254, 88a, 8h
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ADD64 r8, r5, r7
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ST r8, r254, 8a, 8h
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LD r12, r254, 80a, 8h
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LD r1, r254, 32a, 8h
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SUB64 r3, r1, r12
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ST r3, r254, 16a, 8h
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LD r7, r254, 88a, 8h
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LD r8, r254, 40a, 8h
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SUB64 r10, r8, r7
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ST r10, r254, 24a, 8h
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ADDI64 r1, r254, 112d
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BMC r9, r1, 32h
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LI64 r4, 0d
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ADDI64 r7, r254, 96d
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ST r4, r254, 96a, 8h
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ST r4, r254, 104a, 8h
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LD r11, r254, 32a, 8h
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LD r12, r254, 96a, 8h
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ADDI64 r7, r254, 48d
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SUB64 r3, r12, r11
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ST r3, r254, 48a, 8h
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LD r8, r254, 40a, 8h
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LD r9, r254, 104a, 8h
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SUB64 r10, r9, r8
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ST r10, r254, 56a, 8h
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ADDI64 r8, r7, 16d
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BMC r6, r8, 16h
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LD r5, r254, 112a, 8h
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LD r6, r254, 48a, 8h
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ADD64 r8, r6, r5
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ST r8, r254, 48a, 8h
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LD r12, r254, 120a, 8h
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LD r1, r254, 56a, 8h
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ADD64 r3, r12, r1
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ST r3, r254, 56a, 8h
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LD r8, r254, 128a, 8h
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LD r9, r254, 64a, 8h
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ADD64 r11, r8, r9
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ST r11, r254, 160a, 8h
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LD r3, r254, 152a, 8h
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LD r5, r254, 160a, 8h
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ADD64 r1, r5, r3
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ST r11, r254, 64a, 8h
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LD r3, r254, 136a, 8h
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LD r4, r254, 72a, 8h
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ADD64 r6, r3, r4
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ST r6, r254, 72a, 8h
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LD r10, r254, 64a, 8h
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LD r11, r254, 48a, 8h
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ADDI64 r5, r254, 152d
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ADD64 r2, r10, r11
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ST r2, r254, 152a, 8h
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LD r6, r254, 72a, 8h
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LD r7, r254, 56a, 8h
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ADD64 r9, r6, r7
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ST r9, r254, 160a, 8h
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LD r1, r254, 152a, 8h
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ADD64 r1, r1, r9
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1: ADDI64 r254, r254, 168d
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JALA r0, r31, 0a
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code size: 1226
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code size: 1200
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ret: 10
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status: Ok(())
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@ -32,24 +32,23 @@ fib_iter:
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JMP :2
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1: JALA r0, r31, 0a
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main:
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ADDI64 r254, r254, -18d
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ST r31, r254, 2a, 16h
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LI8 r1, 10b
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ADDI64 r254, r254, -26d
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ST r31, r254, 2a, 24h
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LI8 r32, 10b
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ADDI64 r3, r254, 0d
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ST r1, r254, 0a, 1h
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ST r1, r254, 1a, 1h
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ST r32, r254, 0a, 1h
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ST r32, r254, 1a, 1h
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LD r7, r254, 0a, 1h
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ANDI r2, r7, 255d
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JAL r31, r0, :fib
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CP r32, r1
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LD r1, r254, 1a, 1h
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ANDI r2, r1, 255d
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CP r33, r1
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ANDI r2, r32, 255d
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JAL r31, r0, :fib_iter
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CP r8, r32
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SUB64 r1, r8, r1
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LD r31, r254, 2a, 16h
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ADDI64 r254, r254, 18d
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CP r6, r33
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SUB64 r1, r6, r1
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LD r31, r254, 2a, 24h
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ADDI64 r254, r254, 26d
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JALA r0, r31, 0a
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code size: 375
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code size: 362
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ret: 0
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status: Ok(())
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@ -14,13 +14,13 @@ main:
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JMP :2
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1: ADD64 r2, r7, r9
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MULI64 r1, r7, 1024d
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ADD64 r3, r1, r5
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BMC r5, r3, 1024h
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ADD64 r7, r5, r1
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BMC r5, r7, 1024h
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CP r7, r2
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JMP :3
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0: ADD64 r2, r8, r9
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ADD64 r12, r8, r5
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ST r6, r12, 0a, 1h
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ADD64 r8, r5, r8
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ST r6, r8, 0a, 1h
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CP r8, r2
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JMP :4
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2: ADDI64 r254, r254, 10240d
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