forked from AbleOS/holey-bytes
removing specific opts from a fucntion and adding them to the general peepholes
This commit is contained in:
parent
7ef1adf7e2
commit
97eb985a02
156
lang/src/son.rs
156
lang/src/son.rs
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@ -621,11 +621,8 @@ impl Nodes {
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}
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fn iter_peeps(&mut self, mut fuel: usize, stack: &mut Vec<Nid>) {
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debug_assert!(!self.complete);
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debug_assert!(stack.is_empty());
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self.complete = true;
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self.iter()
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.filter_map(|(id, node)| node.kind.is_peeped().then_some(id))
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.collect_into(stack);
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@ -635,6 +632,11 @@ impl Nodes {
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&& let Some(node) = stack.pop()
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{
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fuel -= 1;
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if self[node].outputs.is_empty() {
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self.push_adjacent_nodes(node, stack);
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}
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if self.unlock_remove(node) {
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continue;
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}
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@ -656,11 +658,18 @@ impl Nodes {
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fn push_adjacent_nodes(&mut self, of: Nid, stack: &mut Vec<Nid>) {
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let prev_len = stack.len();
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for &i in self[of].outputs.iter().chain(self[of].inputs.iter()) {
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if self[i].kind.is_peeped() && self[i].lock_rc == 0 {
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for &i in self[of]
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.outputs
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.iter()
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.chain(self[of].inputs.iter())
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.chain(self[of].peep_triggers.iter())
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{
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if self.values[i as usize].is_ok() && self[i].kind.is_peeped() && self[i].lock_rc == 0 {
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stack.push(i);
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}
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}
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self[of].peep_triggers = Vc::default();
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stack.iter().skip(prev_len).for_each(|&n| self.lock(n));
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}
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@ -877,6 +886,11 @@ impl Nodes {
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let mut cursor = n;
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let class = self.aclass_index(self[cursor].inputs[2]);
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if self[class.1].kind != Kind::Stck {
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new_inps.push(n);
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continue;
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}
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cursor = self[cursor].inputs[3];
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while cursor != MEM {
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if self.aclass_index(self[cursor].inputs[2]) != class
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@ -927,9 +941,15 @@ impl Nodes {
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};
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'eliminate: {
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break 'eliminate;
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if self[target].outputs.is_empty() {
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break 'eliminate;
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}
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if self[value].kind != Kind::Load || self[value].outputs.as_slice() != [target]
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{
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for &ele in self[value].outputs.clone().iter().filter(|&&n| n != target) {
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self[ele].peep_triggers.push(target);
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}
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break 'eliminate;
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}
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@ -1038,7 +1058,7 @@ impl Nodes {
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return Some(store);
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}
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return Some(self.modify_input(store, 1, self[target].inputs[1]));
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return Some(self.modify_input(store, 1, value));
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}
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}
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K::Load => {
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@ -1383,117 +1403,6 @@ impl Nodes {
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dominated = self.idom(dominated);
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}
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}
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fn eliminate_stack_temporaries(&mut self) {
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'o: for stack in self[MEM].outputs.clone() {
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if self.values[stack as usize].is_err() || self[stack].kind != Kind::Stck {
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continue;
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}
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let mut full_read_into = None;
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let mut unidentifed = Vc::default();
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for &o in self[stack].outputs.iter() {
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match self[o].kind {
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Kind::Load
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if self[o].ty == self[stack].ty
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&& self[o].outputs.iter().all(|&n| self[n].kind == Kind::Stre)
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&& let mut full_stores = self[o].outputs.iter().filter(|&&n| {
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self[n].kind == Kind::Stre && self[n].inputs[1] == o
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})
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&& let Some(&n) = full_stores.next()
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&& full_stores.next().is_none() =>
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{
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if full_read_into.replace((n, self[o].inputs[2])).is_some() {
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continue 'o;
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}
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}
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_ => unidentifed.push(o),
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}
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}
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let Some((dst, last_store)) = full_read_into else { continue };
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let mut saved = Vc::default();
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let mut cursor = last_store;
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let mut first_store = last_store;
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while cursor != MEM && self[cursor].kind == Kind::Stre {
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let mut contact_point = cursor;
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let mut region = self[cursor].inputs[2];
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if let Kind::BinOp { op } = self[region].kind {
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debug_assert_matches!(op, TokenKind::Add | TokenKind::Sub);
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contact_point = region;
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region = self[region].inputs[1]
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}
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if region != stack {
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break;
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}
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let Some(index) = unidentifed.iter().position(|&n| n == contact_point) else {
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continue 'o;
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};
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unidentifed.remove(index);
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saved.push(contact_point);
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first_store = cursor;
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cursor = *self[cursor].inputs.get(3).unwrap_or(&MEM);
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if unidentifed.is_empty() {
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break;
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}
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}
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let region = self[dst].inputs[2];
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// TODO: this can be an offset already due to previous peeps so handle that
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if let &[mcall] = unidentifed.as_slice()
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&& matches!(self[mcall].kind, Kind::Call { .. })
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&& self[mcall].inputs.last() == Some(&stack)
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{
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self.modify_input(mcall, self[mcall].inputs.len() - 1, region);
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self.replace(dst, last_store);
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} else {
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debug_assert_matches!(
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self[last_store].kind,
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Kind::Stre | Kind::Mem,
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"{:?}",
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self[last_store]
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);
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debug_assert_matches!(
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self[first_store].kind,
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Kind::Stre | Kind::Mem,
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"{:?}",
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self[first_store]
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);
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if !unidentifed.is_empty() {
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continue;
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}
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// FIXME: when the loads and stores become parallel we will need to get saved
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// differently
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let mut prev_store = self[dst].inputs[3];
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for mut oper in saved.into_iter().rev() {
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let mut region = region;
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if let Kind::BinOp { op } = self[oper].kind {
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debug_assert_eq!(self[oper].outputs.len(), 1);
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debug_assert_eq!(self[self[oper].outputs[0]].kind, Kind::Stre);
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region = self.new_node(self[oper].ty, Kind::BinOp { op }, [
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VOID,
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region,
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self[oper].inputs[2],
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]);
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oper = self[oper].outputs[0];
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}
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let mut inps = self[oper].inputs.clone();
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debug_assert_eq!(inps.len(), 4);
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inps[2] = region;
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inps[3] = prev_store;
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prev_store = self.new_node(self[oper].ty, Kind::Stre, inps);
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}
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self.replace(dst, prev_store);
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}
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}
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}
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}
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impl ops::Index<Nid> for Nodes {
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@ -1614,6 +1523,7 @@ pub struct Node {
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kind: Kind,
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inputs: Vc,
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outputs: Vc,
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peep_triggers: Vc,
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ty: ty::Id,
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offset: Offset,
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ralloc_backref: RallocBRef,
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@ -1894,7 +1804,6 @@ impl ItemCtx {
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self.scope.clear(&mut self.nodes);
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mem::take(&mut self.ctrl).soft_remove(&mut self.nodes);
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self.nodes.eliminate_stack_temporaries();
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self.nodes.iter_peeps(1000, stack);
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self.nodes.unlock(MEM);
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@ -2199,11 +2108,10 @@ impl<'a> Codegen<'a> {
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vc.push(load);
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}
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}
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let store = self.ci.nodes.new_node_nop(ty, Kind::Stre, vc);
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aclass.last_store.set(store, &mut self.ci.nodes);
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let opted = self.ci.nodes.late_peephole(store).unwrap_or(store);
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aclass.last_store.set_remove(opted, &mut self.ci.nodes);
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opted
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mem::take(&mut aclass.last_store).soft_remove(&mut self.ci.nodes);
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let store = self.ci.nodes.new_node(ty, Kind::Stre, vc);
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aclass.last_store = StrongRef::new(store, &mut self.ci.nodes);
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store
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}
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fn load_mem(&mut self, region: Nid, ty: ty::Id) -> Nid {
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@ -0,0 +1,16 @@
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main:
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ADDI64 r254, r254, -24d
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ADDI64 r2, r254, 16d
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ST r2, r254, 0a, 8h
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LI64 r5, 0d
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LI64 r4, 2d
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ST r5, r254, 8a, 8h
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ST r4, r254, 16a, 8h
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LD r10, r254, 0a, 8h
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ST r5, r10, 0a, 8h
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LD r1, r254, 16a, 8h
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ADDI64 r254, r254, 24d
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JALA r0, r31, 0a
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code size: 150
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ret: 0
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status: Ok(())
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@ -1,24 +1,17 @@
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main:
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ADDI64 r254, r254, -44d
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ST r31, r254, 28a, 16h
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ADDI64 r254, r254, -40d
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ST r31, r254, 24a, 16h
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LI64 r32, 1d
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ADDI64 r2, r254, 0d
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ST r32, r254, 0a, 8h
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LI64 r8, 2d
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ST r8, r254, 8a, 8h
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LI64 r11, 4d
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ST r11, r254, 16a, 8h
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LI64 r5, 2d
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ST r5, r254, 8a, 8h
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LI64 r8, 4d
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ST r8, r254, 16a, 8h
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JAL r31, r0, :pass
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LI8 r10, 0b
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ST r10, r254, 24a, 1h
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ST r10, r254, 25a, 1h
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LI16 r12, 511h
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ST r12, r254, 26a, 1h
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LI16 r4, 1h
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ST r4, r254, 27a, 1h
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ADD64 r1, r1, r32
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LD r31, r254, 28a, 16h
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ADDI64 r254, r254, 44d
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LD r31, r254, 24a, 16h
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ADDI64 r254, r254, 40d
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JALA r0, r31, 0a
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pass:
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LD r4, r2, 8a, 8h
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@ -29,6 +22,6 @@ pass:
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LD r1, r10, 0a, 8h
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ADD64 r1, r1, r9
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JALA r0, r31, 0a
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code size: 294
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code size: 231
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ret: 8
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status: Ok(())
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@ -2,8 +2,8 @@ cond:
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LI64 r1, 0d
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JALA r0, r31, 0a
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main:
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ADDI64 r254, r254, -16d
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ST r31, r254, 8a, 8h
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ADDI64 r254, r254, -8d
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ST r31, r254, 0a, 8h
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JAL r31, r0, :cond
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LI64 r5, 0d
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CP r7, r5
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@ -12,10 +12,9 @@ main:
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CP r1, r5
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JMP :1
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0: LI64 r1, 2d
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1: ST r1, r254, 0a, 8h
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LD r31, r254, 8a, 8h
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ADDI64 r254, r254, 16d
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1: LD r31, r254, 0a, 8h
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ADDI64 r254, r254, 8d
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JALA r0, r31, 0a
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code size: 147
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code size: 134
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ret: 0
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status: Ok(())
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@ -1,23 +1,19 @@
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main:
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ADDI64 r254, r254, -31d
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ADDI64 r254, r254, -16d
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LI64 r1, 10d
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ADDI64 r4, r254, 15d
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ST r1, r254, 15a, 8h
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ADDI64 r4, r254, 0d
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ST r1, r254, 0a, 8h
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LI64 r7, 20d
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ST r7, r254, 23a, 8h
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ST r7, r254, 8a, 8h
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LI64 r6, 6d
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LI64 r5, 5d
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LI64 r2, 1d
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LD r3, r4, 0a, 16h
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ECA
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LRA r5, r0, :arbitrary text
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ADDI64 r7, r254, 0d
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BMC r5, r7, 15h
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LI64 r1, 0d
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ADDI64 r254, r254, 31d
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ADDI64 r254, r254, 16d
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JALA r0, r31, 0a
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ev: Ecall
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code size: 190
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code size: 152
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ret: 0
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status: Ok(())
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@ -22,22 +22,19 @@ scalar_values:
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LI64 r1, 0d
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JALA r0, r31, 0a
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structs:
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ADDI64 r254, r254, -48d
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LI64 r3, 5d
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ST r3, r254, 0a, 8h
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ST r3, r254, 8a, 8h
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LD r7, r254, 0a, 8h
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ADDI64 r9, r7, 15d
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ST r9, r254, 24a, 8h
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LI64 r8, 20d
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ST r8, r254, 32a, 8h
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LI64 r9, 0d
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LD r3, r254, 24a, 8h
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ST r8, r254, 16a, 8h
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ST r9, r254, 40a, 8h
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SUB64 r1, r3, r8
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ADDI64 r254, r254, 48d
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ADDI64 r254, r254, -32d
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LI64 r2, 5d
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ST r2, r254, 16a, 8h
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ST r2, r254, 24a, 8h
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LD r6, r254, 16a, 8h
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ADDI64 r8, r6, 15d
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ST r8, r254, 0a, 8h
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LI64 r7, 20d
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ST r7, r254, 8a, 8h
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LD r1, r254, 0a, 8h
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SUB64 r1, r1, r7
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ADDI64 r254, r254, 32d
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JALA r0, r31, 0a
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code size: 346
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code size: 310
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ret: 0
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status: Ok(())
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@ -2,31 +2,31 @@ main:
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ADDI64 r254, r254, -152d
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LI8 r1, 0b
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LI8 r3, 1b
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ST r1, r254, 148a, 1h
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ST r3, r254, 144a, 1h
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ST r1, r254, 149a, 1h
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ST r3, r254, 145a, 1h
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ST r1, r254, 150a, 1h
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ST r3, r254, 146a, 1h
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ST r1, r254, 151a, 1h
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ST r3, r254, 147a, 1h
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LD r1, r254, 148a, 1h
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LD r4, r254, 144a, 1h
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ST r1, r254, 132a, 1h
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ST r3, r254, 128a, 1h
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ST r1, r254, 133a, 1h
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ST r3, r254, 129a, 1h
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ST r1, r254, 134a, 1h
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ST r3, r254, 130a, 1h
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ST r1, r254, 135a, 1h
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ST r3, r254, 131a, 1h
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LD r1, r254, 132a, 1h
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LD r4, r254, 128a, 1h
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ADD8 r5, r4, r1
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LD r8, r254, 145a, 1h
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LD r9, r254, 149a, 1h
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ST r5, r254, 148a, 1h
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LD r8, r254, 129a, 1h
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LD r9, r254, 133a, 1h
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ST r5, r254, 132a, 1h
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ADD8 r12, r9, r8
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LD r4, r254, 146a, 1h
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LD r5, r254, 150a, 1h
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ST r12, r254, 149a, 1h
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LD r4, r254, 130a, 1h
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LD r5, r254, 134a, 1h
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ST r12, r254, 133a, 1h
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ADD8 r7, r5, r4
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ST r7, r254, 150a, 1h
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ST r3, r254, 151a, 1h
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LD r12, r254, 149a, 1h
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LD r1, r254, 150a, 1h
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ST r7, r254, 134a, 1h
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ST r3, r254, 135a, 1h
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LD r12, r254, 133a, 1h
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LD r1, r254, 134a, 1h
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ADD8 r4, r1, r12
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LD r5, r254, 148a, 1h
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LD r5, r254, 132a, 1h
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ADD8 r7, r5, r4
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LI8 r9, 4b
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ADD8 r1, r7, r3
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@ -36,61 +36,61 @@ main:
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LI64 r1, 1008d
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JMP :1
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0: LI64 r6, 1d
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ADDI64 r5, r254, 112d
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ST r6, r254, 112a, 8h
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ADDI64 r5, r254, 80d
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ST r6, r254, 80a, 8h
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LI64 r9, 2d
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ST r9, r254, 120a, 8h
|
||||
ST r9, r254, 88a, 8h
|
||||
LI64 r2, 3d
|
||||
ADDI64 r1, r254, 96d
|
||||
ST r2, r254, 64a, 8h
|
||||
ADDI64 r1, r254, 64d
|
||||
ST r2, r254, 48a, 8h
|
||||
LI64 r6, 4d
|
||||
LI64 r2, 0d
|
||||
BMC r5, r1, 16h
|
||||
ST r6, r254, 72a, 8h
|
||||
ST r2, r254, 80a, 8h
|
||||
LD r11, r254, 96a, 8h
|
||||
LD r1, r254, 64a, 8h
|
||||
ST r2, r254, 88a, 8h
|
||||
ST r6, r254, 56a, 8h
|
||||
ST r2, r254, 0a, 8h
|
||||
LD r11, r254, 64a, 8h
|
||||
LD r1, r254, 48a, 8h
|
||||
ST r2, r254, 8a, 8h
|
||||
ADD64 r4, r1, r11
|
||||
LD r7, r254, 104a, 8h
|
||||
LD r2, r254, 80a, 8h
|
||||
ST r4, r254, 32a, 8h
|
||||
LD r7, r254, 72a, 8h
|
||||
LD r2, r254, 0a, 8h
|
||||
ST r4, r254, 96a, 8h
|
||||
ADD64 r12, r7, r6
|
||||
SUB64 r3, r2, r1
|
||||
ADDI64 r8, r254, 0d
|
||||
ST r12, r254, 40a, 8h
|
||||
ADDI64 r8, r254, 16d
|
||||
ST r12, r254, 104a, 8h
|
||||
SUB64 r2, r1, r11
|
||||
ST r3, r254, 0a, 8h
|
||||
ST r3, r254, 16a, 8h
|
||||
LI64 r9, -4d
|
||||
ST r2, r254, 48a, 8h
|
||||
ST r2, r254, 112a, 8h
|
||||
SUB64 r7, r6, r7
|
||||
ST r9, r254, 8a, 8h
|
||||
ST r9, r254, 24a, 8h
|
||||
ADDI64 r8, r8, 16d
|
||||
ST r7, r254, 56a, 8h
|
||||
ST r7, r254, 120a, 8h
|
||||
BMC r5, r8, 16h
|
||||
LD r6, r254, 32a, 8h
|
||||
LD r8, r254, 0a, 8h
|
||||
ADD64 r9, r8, r6
|
||||
LD r11, r254, 8a, 8h
|
||||
LD r1, r254, 40a, 8h
|
||||
ST r9, r254, 0a, 8h
|
||||
ADD64 r4, r1, r11
|
||||
LD r6, r254, 96a, 8h
|
||||
LD r8, r254, 16a, 8h
|
||||
LD r9, r254, 48a, 8h
|
||||
ST r4, r254, 8a, 8h
|
||||
ADD64 r9, r8, r6
|
||||
LD r11, r254, 24a, 8h
|
||||
LD r1, r254, 104a, 8h
|
||||
ST r9, r254, 16a, 8h
|
||||
ADD64 r4, r1, r11
|
||||
LD r8, r254, 32a, 8h
|
||||
LD r9, r254, 112a, 8h
|
||||
ST r4, r254, 24a, 8h
|
||||
ADD64 r12, r9, r8
|
||||
LD r2, r254, 24a, 8h
|
||||
ST r12, r254, 16a, 8h
|
||||
LD r2, r254, 40a, 8h
|
||||
ST r12, r254, 32a, 8h
|
||||
ADD64 r12, r2, r7
|
||||
ST r12, r254, 24a, 8h
|
||||
LD r7, r254, 0a, 8h
|
||||
LD r9, r254, 16a, 8h
|
||||
ST r12, r254, 40a, 8h
|
||||
LD r7, r254, 16a, 8h
|
||||
LD r9, r254, 32a, 8h
|
||||
ADD64 r11, r9, r7
|
||||
LD r1, r254, 8a, 8h
|
||||
ST r11, r254, 128a, 8h
|
||||
LD r1, r254, 24a, 8h
|
||||
ST r11, r254, 136a, 8h
|
||||
ADD64 r6, r1, r12
|
||||
ST r6, r254, 136a, 8h
|
||||
LD r7, r254, 128a, 8h
|
||||
ST r6, r254, 144a, 8h
|
||||
LD r7, r254, 136a, 8h
|
||||
ADD64 r1, r7, r6
|
||||
1: ADDI64 r254, r254, 152d
|
||||
JALA r0, r31, 0a
|
||||
|
|
|
@ -1,25 +1,23 @@
|
|||
main:
|
||||
ADDI64 r254, r254, -80d
|
||||
ST r31, r254, 48a, 32h
|
||||
LI64 r2, 4d
|
||||
ADDI64 r32, r254, 32d
|
||||
ST r2, r254, 32a, 8h
|
||||
LI64 r33, 3d
|
||||
ST r33, r254, 40a, 8h
|
||||
ADDI64 r34, r254, 0d
|
||||
LD r3, r32, 0a, 16h
|
||||
ADDI64 r254, r254, -56d
|
||||
ST r31, r254, 32a, 24h
|
||||
LI64 r3, 4d
|
||||
ADDI64 r2, r254, 16d
|
||||
ST r3, r254, 16a, 8h
|
||||
LI64 r32, 3d
|
||||
ST r32, r254, 24a, 8h
|
||||
ADDI64 r33, r254, 0d
|
||||
LD r3, r2, 0a, 16h
|
||||
JAL r31, r0, :odher_pass
|
||||
ST r1, r254, 0a, 16h
|
||||
ADDI64 r11, r254, 16d
|
||||
BMC r32, r11, 16h
|
||||
LD r4, r254, 8a, 8h
|
||||
JNE r4, r33, :0
|
||||
CP r2, r34
|
||||
LD r2, r254, 8a, 8h
|
||||
JNE r2, r32, :0
|
||||
CP r2, r33
|
||||
JAL r31, r0, :pass
|
||||
JMP :1
|
||||
0: LI64 r1, 0d
|
||||
1: LD r31, r254, 48a, 32h
|
||||
ADDI64 r254, r254, 80d
|
||||
1: LD r31, r254, 32a, 24h
|
||||
ADDI64 r254, r254, 56d
|
||||
JALA r0, r31, 0a
|
||||
odher_pass:
|
||||
ADDI64 r254, r254, -16d
|
||||
|
@ -31,6 +29,6 @@ odher_pass:
|
|||
pass:
|
||||
LD r1, r2, 0a, 8h
|
||||
JALA r0, r31, 0a
|
||||
code size: 321
|
||||
code size: 305
|
||||
ret: 4
|
||||
status: Ok(())
|
||||
|
|
|
@ -14,32 +14,30 @@ main:
|
|||
ADDI64 r254, r254, 24d
|
||||
JALA r0, r31, 0a
|
||||
maina:
|
||||
ADDI64 r254, r254, -44d
|
||||
ST r31, r254, 36a, 8h
|
||||
ADDI64 r6, r254, 32d
|
||||
ADDI64 r254, r254, -36d
|
||||
ST r31, r254, 28a, 8h
|
||||
ADDI64 r5, r254, 24d
|
||||
JAL r31, r0, :small_struct
|
||||
ST r1, r254, 32a, 4h
|
||||
ST r1, r254, 24a, 4h
|
||||
LI8 r11, 0b
|
||||
ADDI64 r10, r254, 24d
|
||||
ST r11, r254, 24a, 1h
|
||||
ST r11, r254, 25a, 1h
|
||||
ST r11, r254, 26a, 1h
|
||||
ADDI64 r10, r254, 0d
|
||||
ST r11, r254, 0a, 1h
|
||||
ST r11, r254, 1a, 1h
|
||||
ST r11, r254, 2a, 1h
|
||||
LI8 r4, 3b
|
||||
ST r4, r254, 27a, 1h
|
||||
ST r4, r254, 3a, 1h
|
||||
LI8 r7, 1b
|
||||
ST r7, r254, 28a, 1h
|
||||
ST r11, r254, 29a, 1h
|
||||
ST r11, r254, 30a, 1h
|
||||
ST r11, r254, 31a, 1h
|
||||
ADDI64 r2, r254, 0d
|
||||
BMC r10, r2, 8h
|
||||
ADDI64 r5, r2, 8d
|
||||
ADDI64 r4, r254, 16d
|
||||
BMC r10, r5, 8h
|
||||
ST r7, r254, 4a, 1h
|
||||
ST r11, r254, 5a, 1h
|
||||
ST r11, r254, 6a, 1h
|
||||
ST r11, r254, 7a, 1h
|
||||
ADDI64 r1, r254, 8d
|
||||
BMC r10, r1, 8h
|
||||
ADDI64 r4, r1, 8d
|
||||
BMC r10, r4, 8h
|
||||
LD r1, r2, 0a, 16h
|
||||
LD r31, r254, 36a, 8h
|
||||
ADDI64 r254, r254, 44d
|
||||
LD r1, r1, 0a, 16h
|
||||
LD r31, r254, 28a, 8h
|
||||
ADDI64 r254, r254, 36d
|
||||
JALA r0, r31, 0a
|
||||
small_struct:
|
||||
ADDI64 r254, r254, -4d
|
||||
|
@ -50,6 +48,6 @@ small_struct:
|
|||
LD r1, r3, 0a, 4h
|
||||
ADDI64 r254, r254, 4d
|
||||
JALA r0, r31, 0a
|
||||
code size: 514
|
||||
code size: 498
|
||||
ret: 2
|
||||
status: Ok(())
|
||||
|
|
Loading…
Reference in a new issue