forked from koniifer/ableos
Added relaxed relative 16 bit instructions
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3e4095da6f
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2f8612c6d2
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@ -1,64 +1,69 @@
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// OPCODE, MNEMONIC, TYPE, DOC;
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0, UN, N, "Cause an unreachable code trap" ;
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1, TX, N, "Termiante execution" ;
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2, NOP, N, "Do nothing" ;
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0, UN, N, "Cause an unreachable code trap" ;
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1, TX, N, "Termiante execution" ;
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2, NOP, N, "Do nothing" ;
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3, ADD, RRR, "Addition" ;
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4, SUB, RRR, "Subtraction" ;
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5, MUL, RRR, "Multiplication" ;
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6, AND, RRR, "Bitand" ;
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7, OR, RRR, "Bitor" ;
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8, XOR, RRR, "Bitxor" ;
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9, SL, RRR, "Unsigned left bitshift" ;
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10, SR, RRR, "Unsigned right bitshift" ;
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11, SRS, RRR, "Signed right bitshift" ;
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12, CMP, RRR, "Signed comparsion" ;
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13, CMPU, RRR, "Unsigned comparsion" ;
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14, DIR, RRRR, "Merged divide-remainder" ;
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15, NOT, RR, "Logical negation" ;
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16, ADDI, RRD, "Addition with immediate" ;
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17, MULI, RRD, "Multiplication with immediate" ;
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18, ANDI, RRD, "Bitand with immediate" ;
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19, ORI, RRD, "Bitor with immediate" ;
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20, XORI, RRD, "Bitxor with immediate" ;
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21, SLI, RRW, "Unsigned left bitshift with immedidate";
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22, SRI, RRW, "Unsigned right bitshift with immediate";
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23, SRSI, RRW, "Signed right bitshift with immediate" ;
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24, CMPI, RRD, "Signed compare with immediate" ;
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25, CMPUI, RRD, "Unsigned compare with immediate" ;
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3, ADD, RRR, "Addition" ;
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4, SUB, RRR, "Subtraction" ;
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5, MUL, RRR, "Multiplication" ;
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6, AND, RRR, "Bitand" ;
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7, OR, RRR, "Bitor" ;
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8, XOR, RRR, "Bitxor" ;
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9, SL, RRR, "Unsigned left bitshift" ;
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10, SR, RRR, "Unsigned right bitshift" ;
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11, SRS, RRR, "Signed right bitshift" ;
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12, CMP, RRR, "Signed comparsion" ;
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13, CMPU, RRR, "Unsigned comparsion" ;
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14, DIR, RRRR, "Merged divide-remainder" ;
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15, NOT, RR, "Logical negation" ;
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16, ADDI, RRD, "Addition with immediate" ;
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17, MULI, RRD, "Multiplication with immediate" ;
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18, ANDI, RRD, "Bitand with immediate" ;
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19, ORI, RRD, "Bitor with immediate" ;
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20, XORI, RRD, "Bitxor with immediate" ;
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21, SLI, RRW, "Unsigned left bitshift with immedidate";
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22, SRI, RRW, "Unsigned right bitshift with immediate";
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23, SRSI, RRW, "Signed right bitshift with immediate" ;
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24, CMPI, RRD, "Signed compare with immediate" ;
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25, CMPUI, RRD, "Unsigned compare with immediate" ;
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26, CP, RR, "Copy register" ;
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27, SWA, RR, "Swap registers" ;
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28, LI, RD, "Load immediate" ;
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29, LRA, RRO, "Load relative address" ;
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30, LD, RRAH, "Load from absolute address" ;
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31, ST, RRAH, "Store to absolute address" ;
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32, LDR, RROH, "Load from relative address" ;
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33, STR, RROH, "Store to absolute address" ;
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34, BMC, RRH, "Copy block of memory" ;
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35, BRC, RRB, "Copy register block" ;
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26, CP, RR, "Copy register" ;
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27, SWA, RR, "Swap registers" ;
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28, LI, RD, "Load immediate" ;
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29, LRA, RRO, "Load relative address" ;
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30, LD, RRAH, "Load from absolute address" ;
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31, ST, RRAH, "Store to absolute address" ;
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32, LDR, RROH, "Load from relative address" ;
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33, STR, RROH, "Store to relative address" ;
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34, BMC, RRH, "Copy block of memory" ;
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35, BRC, RRB, "Copy register block" ;
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36, JMP, A, "Absolute jump" ;
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37, JMPR, O, "Relative jump" ;
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38, JAL, RRA, "Linking absolute jump" ;
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39, JALR, RRO, "Linking relative jump" ;
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40, JEQ, RRP, "Branch on equal" ;
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41, JNE, RRP, "Branch on nonequal" ;
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42, JLT, RRP, "Branch on lesser-than (signed)" ;
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43, JGT, RRP, "Branch on greater-than (signed)" ;
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44, JLTU, RRP, "Branch on lesser-than (unsigned)" ;
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45, JGTU, RRP, "Branch on greater-than (unsigned)" ;
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46, ECALL, N, "Issue ecall trap" ;
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36, JMP, A, "Absolute jump" ;
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37, JMPR, O, "Relative jump" ;
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38, JAL, RRA, "Linking absolute jump" ;
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39, JALR, RRO, "Linking relative jump" ;
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40, JEQ, RRP, "Branch on equal" ;
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41, JNE, RRP, "Branch on nonequal" ;
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42, JLT, RRP, "Branch on lesser-than (signed)" ;
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43, JGT, RRP, "Branch on greater-than (signed)" ;
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44, JLTU, RRP, "Branch on lesser-than (unsigned)" ;
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45, JGTU, RRP, "Branch on greater-than (unsigned)" ;
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46, ECALL, N, "Issue ecall trap" ;
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47, ADDF, RRR, "Floating addition" ;
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48, SUBF, RRR, "Floating subtraction" ;
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49, MULF, RRR, "Floating multiply" ;
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50, DIRF, RRRR, "Merged floating divide-remainder" ;
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51, FMAF, RRRR, "Fused floating multiply-add" ;
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52, NEGF, RR, "Floating sign negation" ;
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53, ITF, RR, "Int to float" ;
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54, FTI, RR, "Float to int" ;
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47, ADDF, RRR, "Floating addition" ;
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48, SUBF, RRR, "Floating subtraction" ;
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49, MULF, RRR, "Floating multiply" ;
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50, DIRF, RRRR, "Merged floating divide-remainder" ;
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51, FMAF, RRRR, "Fused floating multiply-add" ;
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52, NEGF, RR, "Floating sign negation" ;
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53, ITF, RR, "Int to float" ;
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54, FTI, RR, "Float to int" ;
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55, ADDFI, RRD, "Floating addition with immediate" ;
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56, MULFI, RRD, "Floating multiplication with immediate";
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55, ADDFI, RRD, "Floating addition with immediate" ;
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56, MULFI, RRD, "Floating multiplication with immediate";
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57, LRA16 , RRP, "Load relative immediate (16 bit)" ;
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58, LDR16 , RRPH, "Load from relative address (16 bit)" ;
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59, STR16 , RRPH, "Store to relative address (16 bit)" ;
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60, JMPR16, P, "Relative jump (16 bit)" ;
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@ -35,6 +35,7 @@ define_items! {
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OpsRRD (OpR, OpR, OpD ),
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OpsRRAH (OpR, OpR, OpA, OpH),
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OpsRROH (OpR, OpR, OpO, OpH),
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OpsRRPH (OpR, OpR, OpP, OpH),
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OpsRRO (OpR, OpR, OpO ),
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OpsRRP (OpR, OpR, OpP ),
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}
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@ -42,6 +43,7 @@ define_items! {
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unsafe impl BytecodeItem for OpA {}
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unsafe impl BytecodeItem for OpB {}
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unsafe impl BytecodeItem for OpO {}
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unsafe impl BytecodeItem for OpP {}
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unsafe impl BytecodeItem for () {}
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::with_builtin_macros::with_builtin! {
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@ -12,8 +12,8 @@ use {
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crate::mem::{addr::AddressOp, Address},
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core::{cmp::Ordering, mem::size_of, ops},
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hbbytecode::{
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BytecodeItem, OpA, OpO, OpsRD, OpsRR, OpsRRAH, OpsRRB, OpsRRD, OpsRRH, OpsRRO, OpsRROH,
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OpsRRP, OpsRRR, OpsRRRR, OpsRRW,
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BytecodeItem, OpA, OpO, OpP, OpsRD, OpsRR, OpsRRAH, OpsRRB, OpsRRD, OpsRRH, OpsRRO,
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OpsRROH, OpsRRP, OpsRRPH, OpsRRR, OpsRRRR, OpsRRW,
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},
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};
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@ -163,64 +163,20 @@ where
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LD => {
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// Load. If loading more than register size, continue on adjecent registers
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let OpsRRAH(dst, base, off, count) = self.decode();
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let n: u8 = match dst {
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0 => 1,
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_ => 0,
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};
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self.memory.load(
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self.ldst_addr_uber(dst, base, off, count, n)?,
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self.registers
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.as_mut_ptr()
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.add(usize::from(dst) + usize::from(n))
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.cast(),
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usize::from(count).wrapping_sub(n.into()),
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)?;
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self.load(dst, base, off, count)?;
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}
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ST => {
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// Store. Same rules apply as to LD
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let OpsRRAH(dst, base, off, count) = self.decode();
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self.memory.store(
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self.ldst_addr_uber(dst, base, off, count, 0)?,
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self.registers.as_ptr().add(usize::from(dst)).cast(),
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count.into(),
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)?;
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self.store(dst, base, off, count)?;
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}
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LDR => {
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let OpsRROH(dst, base, off, count) = self.decode();
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let n: u8 = match dst {
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0 => 1,
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_ => 0,
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};
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self.memory.load(
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self.ldst_addr_uber(
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dst,
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base,
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u64::from(off).wrapping_add(self.pc.get()),
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count,
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n,
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)?,
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self.registers
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.as_mut_ptr()
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.add(usize::from(dst) + usize::from(n))
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.cast(),
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usize::from(count).wrapping_sub(n.into()),
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)?;
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self.load(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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STR => {
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let OpsRROH(dst, base, off, count) = self.decode();
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self.memory.store(
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self.ldst_addr_uber(
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dst,
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base,
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u64::from(off).wrapping_add(self.pc.get()),
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count,
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0,
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)?,
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self.registers.as_ptr().add(usize::from(dst)).cast(),
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count.into(),
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)?;
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self.store(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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BMC => {
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const INS_SIZE: usize = size_of::<OpsRRH>() + 1;
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@ -341,6 +297,19 @@ where
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}
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ADDFI => self.binary_op_imm::<f64>(ops::Add::add),
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MULFI => self.binary_op_imm::<f64>(ops::Mul::mul),
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LRA16 => {
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let OpsRRP(tg, reg, imm) = self.decode();
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self.write_reg(tg, self.rel_addr(reg, imm).get());
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}
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LDR16 => {
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let OpsRRPH(dst, base, off, count) = self.decode();
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self.load(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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STR16 => {
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let OpsRRPH(dst, base, off, count) = self.decode();
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self.store(dst, base, u64::from(off).wrapping_add(self.pc.get()), count)?;
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}
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JMPR16 => self.pc = self.pc.wrapping_add(self.decode::<OpP>()),
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op => return Err(VmRunError::InvalidOpcode(op)),
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}
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}
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@ -363,6 +332,49 @@ where
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data
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}
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/// Load
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#[inline(always)]
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unsafe fn load(
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&mut self,
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dst: u8,
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base: u8,
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offset: u64,
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count: u16,
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) -> Result<(), VmRunError> {
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let n: u8 = match dst {
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0 => 1,
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_ => 0,
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};
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self.memory.load(
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self.ldst_addr_uber(dst, base, offset, count, n)?,
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self.registers
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.as_mut_ptr()
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.add(usize::from(dst) + usize::from(n))
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.cast(),
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usize::from(count).wrapping_sub(n.into()),
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)?;
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Ok(())
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}
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/// Store
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#[inline(always)]
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unsafe fn store(
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&mut self,
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dst: u8,
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base: u8,
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offset: u64,
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count: u16,
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) -> Result<(), VmRunError> {
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self.memory.store(
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self.ldst_addr_uber(dst, base, offset, count, 0)?,
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self.registers.as_ptr().add(usize::from(dst)).cast(),
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count.into(),
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)?;
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Ok(())
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}
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/// Perform binary operating over two registers
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#[inline(always)]
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unsafe fn binary_op<T: ValueVariant>(&mut self, op: impl Fn(T, T) -> T) {
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