forked from koniifer/ableos
Termination instruction
This commit is contained in:
parent
4530ff049e
commit
eadf9e0a1f
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@ -33,7 +33,7 @@ pub struct Assembler {
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impl Default for Assembler {
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impl Default for Assembler {
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fn default() -> Self {
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fn default() -> Self {
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Self {
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Self {
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buf: vec![0; 3],
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buf: vec![0; 4],
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sub: Default::default(),
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sub: Default::default(),
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}
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}
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}
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}
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@ -13,15 +13,15 @@
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static_assert(CHAR_BIT == 8, "Cursed architectures are not supported");
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static_assert(CHAR_BIT == 8, "Cursed architectures are not supported");
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enum hbbc_Opcode: uint8_t {
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enum hbbc_Opcode: uint8_t {
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hbbc_Op_NOP , hbbc_Op_ADD , hbbc_Op_SUB , hbbc_Op_MUL , hbbc_Op_AND , hbbc_Op_OR ,
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hbbc_Op_UN , hbbc_Op_TX , hbbc_Op_NOP , hbbc_Op_ADD , hbbc_Op_SUB , hbbc_Op_MUL ,
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hbbc_Op_XOR , hbbc_Op_SL , hbbc_Op_SR , hbbc_Op_SRS , hbbc_Op_CMP , hbbc_Op_CMPU ,
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hbbc_Op_AND , hbbc_Op_OR , hbbc_Op_XOR , hbbc_Op_SL , hbbc_Op_SR , hbbc_Op_SRS ,
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hbbc_Op_DIR , hbbc_Op_NEG , hbbc_Op_NOT , hbbc_Op_ADDI , hbbc_Op_MULI , hbbc_Op_ANDI ,
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hbbc_Op_CMP , hbbc_Op_CMPU , hbbc_Op_DIR , hbbc_Op_NEG , hbbc_Op_NOT , hbbc_Op_ADDI ,
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hbbc_Op_ORI , hbbc_Op_XORI , hbbc_Op_SLI , hbbc_Op_SRI , hbbc_Op_SRSI , hbbc_Op_CMPI ,
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hbbc_Op_MULI , hbbc_Op_ANDI , hbbc_Op_ORI , hbbc_Op_XORI , hbbc_Op_SLI , hbbc_Op_SRI ,
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hbbc_Op_CMPUI , hbbc_Op_CP , hbbc_Op_SWA , hbbc_Op_LI , hbbc_Op_LD , hbbc_Op_ST ,
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hbbc_Op_SRSI , hbbc_Op_CMPI , hbbc_Op_CMPUI , hbbc_Op_CP , hbbc_Op_SWA , hbbc_Op_LI ,
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hbbc_Op_BMC , hbbc_Op_BRC , hbbc_Op_JMP , hbbc_Op_JEQ , hbbc_Op_JNE , hbbc_Op_JLT ,
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hbbc_Op_LD , hbbc_Op_ST , hbbc_Op_BMC , hbbc_Op_BRC , hbbc_Op_JMP , hbbc_Op_JEQ ,
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hbbc_Op_JGT , hbbc_Op_JLTU , hbbc_Op_JGTU , hbbc_Op_ECALL , hbbc_Op_ADDF , hbbc_Op_SUBF ,
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hbbc_Op_JNE , hbbc_Op_JLT , hbbc_Op_JGT , hbbc_Op_JLTU , hbbc_Op_JGTU , hbbc_Op_ECALL ,
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hbbc_Op_MULF , hbbc_Op_DIRF , hbbc_Op_FMAF , hbbc_Op_NEGF , hbbc_Op_ITF , hbbc_Op_FTI ,
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hbbc_Op_ADDF , hbbc_Op_SUBF , hbbc_Op_MULF , hbbc_Op_DIRF , hbbc_Op_FMAF , hbbc_Op_NEGF ,
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hbbc_Op_ADDFI , hbbc_Op_MULFI ,
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hbbc_Op_ITF , hbbc_Op_FTI , hbbc_Op_ADDFI , hbbc_Op_MULFI ,
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} typedef hbbc_Opcode;
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} typedef hbbc_Opcode;
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static_assert(sizeof(hbbc_Opcode) == 1);
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static_assert(sizeof(hbbc_Opcode) == 1);
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@ -62,7 +62,7 @@ macro_rules! invoke_with_def {
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bd(p0: R, p1: I)
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bd(p0: R, p1: I)
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=> [LI],
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=> [LI],
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n()
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n()
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=> [UN, NOP, ECALL],
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=> [UN, TX, NOP, ECALL],
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);
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);
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};
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};
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}
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}
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@ -73,62 +73,63 @@ constmod!(pub opcode(u8) {
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//! Opcode constant module
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//! Opcode constant module
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UN = 0, "N; Raises a trap";
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UN = 0, "N; Raises a trap";
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NOP = 1, "N; Do nothing";
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TX = 1, "N; Terminate execution";
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NOP = 2, "N; Do nothing";
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ADD = 2, "BBB; #0 ← #1 + #2";
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ADD = 3, "BBB; #0 ← #1 + #2";
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SUB = 3, "BBB; #0 ← #1 - #2";
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SUB = 4, "BBB; #0 ← #1 - #2";
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MUL = 4, "BBB; #0 ← #1 × #2";
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MUL = 5, "BBB; #0 ← #1 × #2";
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AND = 5, "BBB; #0 ← #1 & #2";
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AND = 6, "BBB; #0 ← #1 & #2";
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OR = 6, "BBB; #0 ← #1 | #2";
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OR = 7, "BBB; #0 ← #1 | #2";
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XOR = 7, "BBB; #0 ← #1 ^ #2";
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XOR = 8, "BBB; #0 ← #1 ^ #2";
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SL = 8, "BBB; #0 ← #1 « #2";
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SL = 9, "BBB; #0 ← #1 « #2";
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SR = 9, "BBB; #0 ← #1 » #2";
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SR = 10, "BBB; #0 ← #1 » #2";
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SRS = 10, "BBB; #0 ← #1 » #2 (signed)";
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SRS = 11, "BBB; #0 ← #1 » #2 (signed)";
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CMP = 11, "BBB; #0 ← #1 <=> #2";
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CMP = 12, "BBB; #0 ← #1 <=> #2";
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CMPU = 12, "BBB; #0 ← #1 <=> #2 (unsigned)";
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CMPU = 13, "BBB; #0 ← #1 <=> #2 (unsigned)";
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DIR = 13, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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DIR = 14, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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NEG = 14, "BB; #0 ← -#1";
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NEG = 15, "BB; #0 ← -#1";
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NOT = 15, "BB; #0 ← !#1";
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NOT = 16, "BB; #0 ← !#1";
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ADDI = 16, "BBD; #0 ← #1 + imm #2";
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ADDI = 17, "BBD; #0 ← #1 + imm #2";
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MULI = 17, "BBD; #0 ← #1 × imm #2";
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MULI = 18, "BBD; #0 ← #1 × imm #2";
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ANDI = 18, "BBD; #0 ← #1 & imm #2";
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ANDI = 19, "BBD; #0 ← #1 & imm #2";
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ORI = 19, "BBD; #0 ← #1 | imm #2";
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ORI = 20, "BBD; #0 ← #1 | imm #2";
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XORI = 20, "BBD; #0 ← #1 ^ imm #2";
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XORI = 21, "BBD; #0 ← #1 ^ imm #2";
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SLI = 21, "BBW; #0 ← #1 « imm #2";
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SLI = 22, "BBW; #0 ← #1 « imm #2";
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SRI = 22, "BBW; #0 ← #1 » imm #2";
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SRI = 23, "BBW; #0 ← #1 » imm #2";
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SRSI = 23, "BBW; #0 ← #1 » imm #2 (signed)";
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SRSI = 24, "BBW; #0 ← #1 » imm #2 (signed)";
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CMPI = 24, "BBD; #0 ← #1 <=> imm #2";
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CMPI = 25, "BBD; #0 ← #1 <=> imm #2";
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CMPUI = 25, "BBD; #0 ← #1 <=> imm #2 (unsigned)";
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CMPUI = 26, "BBD; #0 ← #1 <=> imm #2 (unsigned)";
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CP = 26, "BB; Copy #0 ← #1";
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CP = 27, "BB; Copy #0 ← #1";
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SWA = 27, "BB; Swap #0 and #1";
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SWA = 28, "BB; Swap #0 and #1";
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LI = 28, "BD; #0 ← imm #1";
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LI = 29, "BD; #0 ← imm #1";
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LD = 29, "BBDB; #0 ← [#1 + imm #3], imm #4 bytes, overflowing";
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LD = 30, "BBDB; #0 ← [#1 + imm #3], imm #4 bytes, overflowing";
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ST = 30, "BBDB; [#1 + imm #3] ← #0, imm #4 bytes, overflowing";
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ST = 31, "BBDB; [#1 + imm #3] ← #0, imm #4 bytes, overflowing";
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BMC = 31, "BBD; [#0] ← [#1], imm #2 bytes";
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BMC = 32, "BBD; [#0] ← [#1], imm #2 bytes";
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BRC = 32, "BBB; #0 ← #1, imm #2 registers";
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BRC = 33, "BBB; #0 ← #1, imm #2 registers";
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JAL = 33, "BD; Copy PC to #0 and unconditional jump [#1 + imm #2]";
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JAL = 34, "BD; Copy PC to #0 and unconditional jump [#1 + imm #2]";
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JEQ = 34, "BBD; if #0 = #1 → jump imm #2";
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JEQ = 35, "BBD; if #0 = #1 → jump imm #2";
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JNE = 35, "BBD; if #0 ≠ #1 → jump imm #2";
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JNE = 36, "BBD; if #0 ≠ #1 → jump imm #2";
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JLT = 36, "BBD; if #0 < #1 → jump imm #2";
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JLT = 37, "BBD; if #0 < #1 → jump imm #2";
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JGT = 37, "BBD; if #0 > #1 → jump imm #2";
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JGT = 38, "BBD; if #0 > #1 → jump imm #2";
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JLTU = 38, "BBD; if #0 < #1 → jump imm #2 (unsigned)";
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JLTU = 39, "BBD; if #0 < #1 → jump imm #2 (unsigned)";
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JGTU = 39, "BBD; if #0 > #1 → jump imm #2 (unsigned)";
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JGTU = 40, "BBD; if #0 > #1 → jump imm #2 (unsigned)";
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ECALL = 40, "N; Issue system call";
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ECALL = 41, "N; Issue system call";
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ADDF = 41, "BBB; #0 ← #1 +. #2";
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ADDF = 42, "BBB; #0 ← #1 +. #2";
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SUBF = 42, "BBB; #0 ← #1 -. #2";
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SUBF = 43, "BBB; #0 ← #1 -. #2";
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MULF = 43, "BBB; #0 ← #1 +. #2";
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MULF = 44, "BBB; #0 ← #1 +. #2";
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DIRF = 44, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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DIRF = 45, "BBBB; #0 ← #2 / #3, #1 ← #2 % #3";
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FMAF = 45, "BBBB; #0 ← (#1 * #2) + #3";
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FMAF = 46, "BBBB; #0 ← (#1 * #2) + #3";
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NEGF = 46, "BB; #0 ← -#1";
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NEGF = 47, "BB; #0 ← -#1";
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ITF = 47, "BB; #0 ← #1 as float";
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ITF = 48, "BB; #0 ← #1 as float";
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FTI = 48, "BB; #0 ← #1 as int";
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FTI = 49, "BB; #0 ← #1 as int";
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ADDFI = 49, "BBD; #0 ← #1 +. imm #2";
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ADDFI = 50, "BBD; #0 ← #1 +. imm #2";
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MULFI = 50, "BBD; #0 ← #1 *. imm #2";
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MULFI = 51, "BBD; #0 ← #1 *. imm #2";
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});
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});
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#[repr(packed)]
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#[repr(packed)]
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@ -100,7 +100,7 @@ where
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loop {
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loop {
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// Check instruction boundary
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// Check instruction boundary
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if self.pc >= self.program_len {
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if self.pc >= self.program_len {
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return Ok(VmRunOk::End);
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return Err(VmRunError::AddrOutOfBounds);
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}
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}
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// Big match
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// Big match
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@ -128,6 +128,10 @@ where
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self.decode::<()>();
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self.decode::<()>();
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return Err(VmRunError::Unreachable);
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return Err(VmRunError::Unreachable);
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}
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}
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TX => {
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self.decode::<()>();
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return Ok(VmRunOk::End);
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}
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NOP => self.decode::<()>(),
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NOP => self.decode::<()>(),
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ADD => self.binary_op(u64::wrapping_add),
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ADD => self.binary_op(u64::wrapping_add),
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SUB => self.binary_op(u64::wrapping_sub),
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SUB => self.binary_op(u64::wrapping_sub),
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@ -10,6 +10,7 @@ use {
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fn main() -> Result<(), Box<dyn std::error::Error>> {
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fn main() -> Result<(), Box<dyn std::error::Error>> {
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let mut prog = vec![];
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let mut prog = vec![];
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stdin().read_to_end(&mut prog)?;
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stdin().read_to_end(&mut prog)?;
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println!("{prog:?}");
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if let Err(e) = validate(&prog) {
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if let Err(e) = validate(&prog) {
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eprintln!("Program validation error: {e:?}");
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eprintln!("Program validation error: {e:?}");
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107
spec.md
107
spec.md
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@ -34,13 +34,14 @@
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- `P ← V`: Set register P to value V
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- `P ← V`: Set register P to value V
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- `[x]`: Address x
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- `[x]`: Address x
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## No-op
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## Program execution control
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- N type
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- N type
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------------:|
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|:------:|:----:|:-----------------------------:|
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| 0 | UN | Trigger unreachable code trap |
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| 0 | UN | Trigger unreachable code trap |
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| 1 | NOP | Do nothing |
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| 1 | TX | Terminate execution |
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| 2 | NOP | Do nothing |
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## Integer binary ops.
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## Integer binary ops.
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- BBB type
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- BBB type
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@ -48,21 +49,21 @@
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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|:------:|:----:|:-----------------------:|
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| 2 | ADD | Wrapping addition |
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| 3 | ADD | Wrapping addition |
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| 3 | SUB | Wrapping subtraction |
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| 4 | SUB | Wrapping subtraction |
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| 4 | MUL | Wrapping multiplication |
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| 5 | MUL | Wrapping multiplication |
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| 5 | AND | Bitand |
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| 6 | AND | Bitand |
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| 6 | OR | Bitor |
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| 7 | OR | Bitor |
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| 7 | XOR | Bitxor |
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| 8 | XOR | Bitxor |
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| 8 | SL | Unsigned left bitshift |
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| 9 | SL | Unsigned left bitshift |
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| 9 | SR | Unsigned right bitshift |
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| 10 | SR | Unsigned right bitshift |
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| 10 | SRS | Signed right bitshift |
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| 11 | SRS | Signed right bitshift |
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### Comparsion
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### Comparsion
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------:|
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|:------:|:----:|:-------------------:|
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| 11 | CMP | Signed comparsion |
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| 12 | CMP | Signed comparsion |
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| 12 | CMPU | Unsigned comparsion |
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| 13 | CMPU | Unsigned comparsion |
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#### Comparsion table
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#### Comparsion table
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| #1 *op* #2 | Result |
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| #1 *op* #2 | Result |
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@ -79,7 +80,7 @@
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:-------------------------------:|
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|:------:|:----:|:-------------------------------:|
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| 13 | DIR | Divide and remainder combinated |
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| 14 | DIR | Divide and remainder combinated |
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### Negations
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### Negations
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- Type BB
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- Type BB
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@ -87,36 +88,36 @@
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:----------------:|
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|:------:|:----:|:----------------:|
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| 14 | NEG | Bit negation |
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| 15 | NEG | Bit negation |
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| 15 | NOT | Logical negation |
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| 16 | NOT | Logical negation |
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## Integer immediate binary ops.
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## Integer immediate binary ops.
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- Type BBD
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- Type BBD
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- `#0 ← #1 <op> imm #2`
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- `#0 ← #1 <op> imm #2`
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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|:------:|:----:|:--------------------:|
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| 16 | ADDI | Wrapping addition |
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| 17 | ADDI | Wrapping addition |
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| 17 | MULI | Wrapping subtraction |
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| 18 | MULI | Wrapping subtraction |
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| 18 | ANDI | Bitand |
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| 19 | ANDI | Bitand |
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| 19 | ORI | Bitor |
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| 20 | ORI | Bitor |
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| 20 | XORI | Bitxor |
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| 21 | XORI | Bitxor |
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### Bitshifts
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### Bitshifts
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- Type BBW
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- Type BBW
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:-----------------------:|
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|:------:|:----:|:-----------------------:|
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| 21 | SLI | Unsigned left bitshift |
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| 22 | SLI | Unsigned left bitshift |
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| 22 | SRI | Unsigned right bitshift |
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| 23 | SRI | Unsigned right bitshift |
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| 23 | SRSI | Signed right bitshift |
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| 24 | SRSI | Signed right bitshift |
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### Comparsion
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### Comparsion
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- Comparsion is the same as when RRR type
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- Comparsion is the same as when RRR type
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:-----:|:-------------------:|
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|:------:|:-----:|:-------------------:|
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| 24 | CMPI | Signed comparsion |
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| 25 | CMPI | Signed comparsion |
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| 25 | CMPUI | Unsigned comparsion |
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| 26 | CMPUI | Unsigned comparsion |
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## Register value set / copy
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## Register value set / copy
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@ -126,7 +127,7 @@
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| Opcode | Name | Action |
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| Opcode | Name | Action |
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|:------:|:----:|:------:|
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|:------:|:----:|:------:|
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| 26 | CP | Copy |
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| 27 | CP | Copy |
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### Swap
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### Swap
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- Type BB
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- Type BB
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|
@ -137,7 +138,7 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:------:|
|
|:------:|:----:|:------:|
|
||||||
| 27 | SWA | Swap |
|
| 28 | SWA | Swap |
|
||||||
|
|
||||||
### Load immediate
|
### Load immediate
|
||||||
- Type BD
|
- Type BD
|
||||||
|
|
@ -145,7 +146,7 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:--------------:|
|
|:------:|:----:|:--------------:|
|
||||||
| 28 | LI | Load immediate |
|
| 29 | LI | Load immediate |
|
||||||
|
|
||||||
## Memory operations
|
## Memory operations
|
||||||
- Type BBDH
|
- Type BBDH
|
||||||
|
|
@ -154,8 +155,8 @@
|
||||||
### Load / Store
|
### Load / Store
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:---------------------------------------:|
|
|:------:|:----:|:---------------------------------------:|
|
||||||
| 29 | LD | `#0 ← [#1 + imm #3], copy imm #4 bytes` |
|
| 30 | LD | `#0 ← [#1 + imm #3], copy imm #4 bytes` |
|
||||||
| 30 | ST | `[#1 + imm #3] ← #0, copy imm #4 bytes` |
|
| 31 | ST | `[#1 + imm #3] ← #0, copy imm #4 bytes` |
|
||||||
|
|
||||||
## Block copy
|
## Block copy
|
||||||
- Block copy source and target can overlap
|
- Block copy source and target can overlap
|
||||||
|
|
@ -165,7 +166,7 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:--------------------------------:|
|
|:------:|:----:|:--------------------------------:|
|
||||||
| 31 | BMC | `[#1] ← [#0], copy imm #2 bytes` |
|
| 32 | BMC | `[#1] ← [#0], copy imm #2 bytes` |
|
||||||
|
|
||||||
### Register copy
|
### Register copy
|
||||||
- Type BBB
|
- Type BBB
|
||||||
|
|
@ -173,7 +174,7 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:--------------------------------:|
|
|:------:|:----:|:--------------------------------:|
|
||||||
| 32 | BRC | `#1 ← #0, copy imm #2 registers` |
|
| 33 | BRC | `#1 ← #0, copy imm #2 registers` |
|
||||||
|
|
||||||
## Control flow
|
## Control flow
|
||||||
|
|
||||||
|
|
@ -182,7 +183,7 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:--------------------------------------------------:|
|
|:------:|:----:|:--------------------------------------------------:|
|
||||||
| 33 | JAL | Save PC past JAL to `#0` and jump at `#1 + imm #2` |
|
| 34 | JAL | Save PC past JAL to `#0` and jump at `#1 + imm #2` |
|
||||||
|
|
||||||
### Conditional jumps
|
### Conditional jumps
|
||||||
- Type BBD
|
- Type BBD
|
||||||
|
|
@ -190,19 +191,19 @@
|
||||||
|
|
||||||
| Opcode | Name | Comparsion |
|
| Opcode | Name | Comparsion |
|
||||||
|:------:|:----:|:------------:|
|
|:------:|:----:|:------------:|
|
||||||
| 34 | JEQ | = |
|
| 35 | JEQ | = |
|
||||||
| 35 | JNE | ≠ |
|
| 36 | JNE | ≠ |
|
||||||
| 36 | JLT | < (signed) |
|
| 37 | JLT | < (signed) |
|
||||||
| 37 | JGT | > (signed) |
|
| 38 | JGT | > (signed) |
|
||||||
| 38 | JLTU | < (unsigned) |
|
| 39 | JLTU | < (unsigned) |
|
||||||
| 39 | JGTU | > (unsigned) |
|
| 40 | JGTU | > (unsigned) |
|
||||||
|
|
||||||
### Environment call
|
### Environment call
|
||||||
- Type N
|
- Type N
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:-----:|:-------------------------------------:|
|
|:------:|:-----:|:-------------------------------------:|
|
||||||
| 40 | ECALL | Cause an trap to the host environment |
|
| 41 | ECALL | Cause an trap to the host environment |
|
||||||
|
|
||||||
## Floating point operations
|
## Floating point operations
|
||||||
- Type BBB
|
- Type BBB
|
||||||
|
|
@ -210,29 +211,29 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:--------------:|
|
|:------:|:----:|:--------------:|
|
||||||
| 41 | ADDF | Addition |
|
| 42 | ADDF | Addition |
|
||||||
| 42 | SUBF | Subtraction |
|
| 43 | SUBF | Subtraction |
|
||||||
| 43 | MULF | Multiplication |
|
| 44 | MULF | Multiplication |
|
||||||
|
|
||||||
### Division-remainder
|
### Division-remainder
|
||||||
- Type BBBB
|
- Type BBBB
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:-------------------------:|
|
|:------:|:----:|:-------------------------:|
|
||||||
| 44 | DIRF | Same as for integer `DIR` |
|
| 45 | DIRF | Same as for integer `DIR` |
|
||||||
|
|
||||||
### Fused Multiply-Add
|
### Fused Multiply-Add
|
||||||
- Type BBBB
|
- Type BBBB
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:---------------------:|
|
|:------:|:----:|:---------------------:|
|
||||||
| 45 | FMAF | `#0 ← (#1 * #2) + #3` |
|
| 46 | FMAF | `#0 ← (#1 * #2) + #3` |
|
||||||
|
|
||||||
### Negation
|
### Negation
|
||||||
- Type BB
|
- Type BB
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:----------:|
|
|:------:|:----:|:----------:|
|
||||||
| 46 | NEGF | `#0 ← -#1` |
|
| 47 | NEGF | `#0 ← -#1` |
|
||||||
|
|
||||||
### Conversion
|
### Conversion
|
||||||
- Type BB
|
- Type BB
|
||||||
|
|
@ -241,8 +242,8 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:----:|:------------:|
|
|:------:|:----:|:------------:|
|
||||||
| 47 | ITF | Int to Float |
|
| 48 | ITF | Int to Float |
|
||||||
| 48 | FTI | Float to Int |
|
| 49 | FTI | Float to Int |
|
||||||
|
|
||||||
## Floating point immediate operations
|
## Floating point immediate operations
|
||||||
- Type BBD
|
- Type BBD
|
||||||
|
|
@ -250,8 +251,8 @@
|
||||||
|
|
||||||
| Opcode | Name | Action |
|
| Opcode | Name | Action |
|
||||||
|:------:|:-----:|:--------------:|
|
|:------:|:-----:|:--------------:|
|
||||||
| 49 | ADDFI | Addition |
|
| 50 | ADDFI | Addition |
|
||||||
| 50 | MULFI | Multiplication |
|
| 51 | MULFI | Multiplication |
|
||||||
|
|
||||||
# Registers
|
# Registers
|
||||||
- There is 255 registers + one zero register (with index 0)
|
- There is 255 registers + one zero register (with index 0)
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue